UPD9971 datasheet(39/112 Pages) RENESAS

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µPD9971

Data Sheet S17455EJ2V0DS

5.3 PLL Block

Figure 5-4 PLL

STPLL1,

STPLL2

MCLK1A[6:0],

MCLK1B[7:0]

MCLK1

MCLKSEL

MCLK2

Audio

master clock

Melody

master clock

MCLKSEL

MCLK2A[4:0],

MCLK2B[7:0]

Selector

CSTRT

CSTRTEN

PLL1

PLL2

This block has the following functions:

• Divides or multiplies clocks input from the outside (which is done by the setting of registers) and generates the

sound generator master clock as well as the audio master clock.

• Selects either the MCLK1 or MCLK2 pin as the clock input pin by using an internal register MCLKSEL or an

external pin CSTRT. (Selection using the CSTRT pin is a special mode. Normally, use the MCLKSEL register.)

• Requires a setting, CSTRTEN bit = high, for validating the selection using the CSTRT pin.

• Inputs the MCLK2 pin to the EVDD level because the pin uses external digital signals as clocks.

• Receives power supply from PLLVDD.

This block generates the audio master clock when the STPLL1 bit is set to the high level, and the sound generator

block master clock when the STPLL2 bit is set to the high level. Each master clock requires the setting of a division

ratio by MCLK1A, MCLK1B, MCLK2A, and MCLK2B registers. The setting has to be performed in accordance with

the input frequency and the sampling frequency.

When the CSTRTEN bit is set to the low level, and when the MCLKSEL bit is set to the low level, the MCLK1 pin is

selected as the clock input pin. In this case, if the MCLKSEL bit is set to the high level, the MCLK2 pin is selected.

When the CSTRTEN bit is set to the high level, and when a specific division ratio is set, a special mode in which

clock input pins are switched by an external pin CSTRT is enabled. For details of the special mode, contact NEC

Electronics.

Normally, use the MCLKSEL register to perform the switching.

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