MPQ2169B

– 6V, DUAL 1.4A/1.4A OR 2A/0.8A SYNC BUCK REGULATOR, AEC-Q100

MPQ2169B Rev. 1.0

MonolithicPower.com

23

12/20/2021

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PCB Layout Guidelines (9)

Efficient

PCB

layout

is

critical

for

stable

operation.

A

4-layer

layout

is

strongly

recommended to improve thermal performance.

For the best results, refer to Figure 6 and follow

the guidelines below:

1. Connect PGND1 and PGND2 together at

PGND.

2. Place the high-current paths (PGND, VIN,

and SW) very close to the device with short,

direct, and wide traces.

3. Place input capacitors on both sides of VIN,

as close to VIN and PGND as possible.

4. Place the decoupling capacitor as close to

VCC and AGND as possible.

5. Keep the switching node (SW) short, and

route it away from the feedback network.

6. Place the external feedback resistors next

to FB.

7. Do not place vias on the FB trace.

8. Connect PGND to a large copper area to

improve thermal performance.

Note:

9) The recommended PCB layout is based on Figure 7 on page

24.

Top Layer

Mid-Layer 1

Mid-Layer 2

Bottom Layer

Figure 6: Recommended PCB Layout