MP5048

– 60V, 15A, 7mΩ RDS(ON) HOT-SWAP INTELLI-FUSE SOLUTION

MP5048 Rev. 1.1

www.MonolithicPower.com

17

4/30/2021

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© 2021 MPS. All Rights Reserved.

Insertion Delay

MP5048

UVLO

VOUT

ON

VCC

VCLREF

SS Limit

VCLREF_NORM

t

Figure 13: MP5048 SS Current Limit

If VOUT drops below 90% of VIN, the current limit

reference is clamped to VBE (660mV with a

negative

temperature

coefficient),

and

the

thermal shutdown threshold is 153°C.

If the CS limit reference configuration current is

8

μA, then the external CLREF voltage depends

on the CLREF external resistor. If the external

CLREF voltage drops below the clamp voltage

(VCLREF_CLAMP), the actual current limit reference

voltage is determined by the external CLREF

voltage.

If VOUT ≥ 90% of VIN, the internal maximum

current limit reference voltage is disabled. The

CS limit reference configuration current ranges

between 8

μA and 26μA (8μA + 18μA), and CS is

limited by the CLREF

’s externally configured

value (typically limited to 2V).

If VCS exceeds the SS limit during start-up, the

power FET gate voltage is regulated to hold the

FET current constant. If the power FET remains

on while VOUT remains below 90% of VIN within

the 200ms maximum soft-start time, the power

FET shuts down when the 200ms time ends. If

the value of the SS limit is higher, the power FET

start-up instantaneous loss is large and a

thermal shutdown is triggered before the 200ms

time ends. In this case, FAULT is driven low (see

Figure 14).

t

VGS

VOUT

FAULT

ON

VCS

600mV

Maximum SS time 200ms

VGS_TH

VSS_LIMT

Thermal

Shutdown

Figure 14: Failed Start-Up Within 200ms

If VOUT drops below 20% of VIN during start-up

and the power FET current is regulated by

VSS_LIMIT for the start-up SCP timer, the power

FET turns off with a fault latch condition, and

FAULT is pulled low.

Current Limit During Normal Operation

When the MP5048 detects that start-up has

finished, the part enters normal operation.

During normal operation, once VCS (which is

configured by an external resistor) exceeds the

normal CLREF threshold, the internal circuit

regulates the gate voltage to hold the power FET

constant. To limit the current, the gate-to-source

voltage must be regulated from 5V to about VTH.

The typical response time is about 14µs. The

output current may have a small overshoot

during this time period.

If the current limit is reached, the internal fault

timer starts. If the output current falls below the

current limit threshold before the end of the over-

current protection (OCP) fault timeout period, the

MP5048 resumes normal operation. If the

current exceeds the fault timeout period, the

power FET latches off and FAULT is pulled low.

The desired current limit during normal operation

is a function of CS

’s external resistor (RCS).

The MP5048 current limit value can exceed the

normal

maximum

load

current,

allowing

tolerances in the current-sense value. The

current limit can be estimated with Equation (2):

CS

CS

CLREF_NORM

LIMIT

R

G

V

I





(2)