ST72344 datasheet(189/191 Pages) STMICROELECTRONICS

189 / 191 page

ST72340, ST72344, ST72345

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16.3 16-bit Timer PWM Mode

In PWM mode, the first PWM pulse is missed after

writing the value FFFCh in the OC1R register

(OC1HR, OC1LR). It leads to either full or no PWM

during a period, depending on the OLVL1 and

OLVL2 settings.

16.4 SCI Wrong Break duration

Description

A single break character is sent by setting and re-

setting the SBK bit in the SCICR2 register. In

some cases, the break character may have a long-

er duration than expected:

- 20 bits instead of 10 bits if M=0

- 22 bits instead of 11 bits if M=1

In the same way, as long as the SBK bit is set,

break characters are sent to the TDO pin. This

may lead to generate one break more than expect-

ed.

Occurrence

The occurrence of the problem is random and pro-

portional to the baudrate. With a transmit frequen-

19200

baud

(fCPU=8MHz and SCI-

BRR=0xC9), the wrong break duration occurrence

is around 1%.

Workaround

If this wrong duration is not compliant with the

communication protocol in the application, soft-

ware can request that an Idle line be generated

before the break character. In this case, the break

duration is always correct assuming the applica-

tion is not doing anything between the idle and the

break. This can be ensured by temporarily disa-

bling interrupts.

The exact sequence is:

- Disable interrupts

- Reset and Set TE (IDLE request)

- Set and Reset SBK (Break Request)

- Re-enable interrupts

16.5 In-Application Programming

Not available on the first silicon revision currently

in production (rev Z). This limitation will be correct-

ed on the next silicon revision. Refer to Table 35

Silicon revision identification.

16.6 Programming of EEPROM data

Description

In user mode, when programming EEPROM data

memory, the read access to the program memory

between E000h and FFFFh can be corrupted.

Impact on application

The EEPROM programming routine must be locat-

ed outside this program memory area.

Any access to the interrupt vector table can result

in an unexpected code being executed, so the in-

terrupts must be masked.

Workaround

The sequence to program the EEPROM data (re-

fer to Section 5.3 on page 19) must be executed

within C000h-DFFFh area or from the RAM. It is as

follows:

set E2LAT bit

write up to 32 bytes in E2PROM area

SIM ; to disable the interrupts

set E2PGM bit

wait for E2PGM=0

RIM ; to enable the interrupts

return to the program memory

16.7 Flash Write/Erase Protection

Not available on the first silicon revision currently

in production (rev Z). This limitation will be correct-

ed on the next silicon revision. Refer to Table 35

Silicon revision identification.

Table 35. Silicon revision identification

Device

Status

Trace code

marked on device

internal sales types

on box label

ST72F344xxxx

ST72F345xxxx

In Production

“xxxxxxxxZ”

72F344xxxx$x2

72F345xxxx$x2

Under qualification

“xxxxxxxxX”

72F344xxxx$x4

72F345xxxx$x4

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