ST72344 datasheet(188/191 Pages) STMICROELECTRONICS

188 / 191 page

ST72340, ST72344, ST72345

188/191

LD PFDDR,A; Write into PFDDR

LD A,#$ff

LD PFOR,A

; Write to PFOR

LD A,PFDR

AND A,#$02

LD Y,A

; store the level after writing to PxOR/

PxDDR

LD A,X

; check for falling edge

cp A,#$02

jrne OUT

TNZ Y

jrne OUT

LD A,#$01

LD sema,A ; set the semaphore to '1' if edge is

detected

RIM

; reset the interrupt mask

LD A,sema ; check the semaphore status

CP A,#$01

jrne OUT

call call_routine; call the interrupt routine

RIM

OUT:

RIM

JP while_loop

.call_routine ; entry to call_routine

PUSH A

PUSH X

PUSH CC

.ext1_rt

; entry to interrupt routine

LD A,#$00

LD sema,A

IRET

16.1.1 Unexpected Reset Fetch

If an interrupt request occurs while a "POP CC" in-

struction is executed, the interrupt controller does

not recognise the source of the interrupt and, by

default, passes the RESET vector address to the

CPU.

Workaround

To solve this issue, a "POP CC" instruction must

always be preceded by a "SIM" instruction.

16.2

Clearing

active

interrupts

outside

interrupt routine

When an active interrupt request occurs at the

same time as the related flag is being cleared, an

unwanted reset may occur.

Note: clearing the related interrupt mask will not

generate an unwanted reset

Concurrent interrupt context

The symptom does not occur when the interrupts

are handled normally, i.e.

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

Perform SIM and RIM operation before and after

resetting an active interrupt request.

Example:

SIM

reset interrupt flag

RIM

Nested interrupt context:

The symptom does not occur when the interrupts

are handled normally, i.e.

when:

– The interrupt flag is cleared within its own inter-

rupt routine

– The interrupt flag is cleared within any interrupt

routine with higher or identical priority level

– The interrupt flag is cleared in any part of the

code while this interrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

PUSH CC

SIM

reset interrupt flag

POP CC

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