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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST72344 датащи(PDF) 182 Page - STMicroelectronics |
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ST72344 датащи(HTML) 182 Page - STMicroelectronics |
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182 / 191 page  ST72340, ST72344, ST72345 182/191 OPTION BYTES (Cont’d) OPTION BYTE 1 OPT7 = RSTC RESET clock cycle selection This option bit selects the number of CPU cycles inserted during the RESET phase and when exit- ing HALT mode. For resonator oscillators, it is ad- vised to select 4096 due to the long crystal stabili- zation time. 0: Reset phase with 4096 CPU cycles 1: Reset phase with 256 CPU cycles OPT6:4 = OSCRANGE[2:0] Oscillator range When the internal RC oscillator is not selected (Option OSC=1), these option bits select the range of the resonator oscillator current source or the ex- ternal clock source. OPT3 = OSC RC Oscillator selection 0: RC oscillator on 1: RC oscillator off OPT2 = DIV2EN PLL Divide by 2 enable 0: PLL division by 2 enabled 1: PLL division by 2 disabled Note: DIV2EN must be kept disabled when PLLx4 is enabled OPT1 = PLLx4x8 PLL Factor selection 0: PLLx4 1: PLLx8 OPT0 = PLLOFF PLL disable 0: PLL enabled 1: PLL disabled (by-passed) These option bits must be configured as described in Table 32 depending on the voltage range and the expected CPU frequency Table 32. List of valid option combinations Note: 1. For a target ratio of x4 between 3.3V - 3.65V, this is the recommended configuration. OSCRANGE 21 0 Typ. frequency range with Resonator LP 1~2MHz 0 0 0 MP 2~4MHz 0 0 1 MS 4~8MHz 0 1 0 HS 8~16MHz 0 1 1 Reserved 1 0 0 External Clock 10 1 11 0 11 1 Target Ratio VDD Option Bits DIV2 EN PLL OFF PLL x4x8 x41) 2.7V - 3.65V x 0 0 x4 3.3V - 5.5V 00 1 x8 1 0 1 |
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