ST72344 datasheet(131/191 Pages) STMICROELECTRONICS

131 / 191 page

ST72340, ST72344, ST72345

131/191

I2C3S INTERFACE (Cont’d)

This process continues until a Stop or Restart

condition occurs.

2. I2C3S attempts to read a word while the CPU is

updating the RAM buffer. To prevent data cor-

ruption, the CPU must switch operation to Word

mode prior to updating a word in the RAM

buffer. Word mode is enabled by software using

the B/W bit in the I2C3SCR2 register. In Word

mode, when the CPU writes the MSB of a word

to address 2n, it is stored in a shadow register

rather than being actually written in RAM. When

the CPU writes the second byte (the LSB) at

address 2n+1, it is directly written in RAM. The

next cycle after the write to address 2n+1, the

MSB is automatically written from the shadow

for a 1 cycle while the CPU is writing a word.

Word mode is disabled by hardware after the

word update is performed. It must be enabled

before each word update by CPU.

Use the following procedure when the ST7 writes

a word in RAM:

1. Disable interrupts

2. Enable Word mode by setting the B/W and

BusyW bits in the I2C3SCR2 register. BusyW

bit is set to 1 when modifying any bits in Control

ally modify BusyW but prevents accidental

clearing of the bit.

3. Write Byte 1 in an even address in RAM. The

byte is not actually written in RAM but in a

shadow register. This address must be within

the I2C RAM buffer of slave addresses 1, 2 or

4. Write Byte 2 in the next higher address in RAM.

This byte is actually written in RAM. During the

next cycle, the shadow register content is writ-

ten in the lower address. The DMA request is

disabled during this cycle.

5. Byte mode resumes automatically after writing

byte 2 and DMA is re-enabled.

6. Enable interrupts

Note: Word mode does not guarantee byte-pair

coherency of words WRITTEN by the I2C master

in RAM and read by the ST7. Byte pair coherency

in this case must be handled by software.

Figure 70. 16-bit Word Write Operation Flowchart

SENDS ADDRESS

AND WRITE BIT

DECODES I2C3SNS ADDRESS

DECODES R/W BIT

SETS WRITE FLAG

SENDS WRITE ADDRESS

SENDS 1 BYTE OF DATA

STOP CONDITION

UPDATES CURRENT ADDRESS-

ISSUES DMA REQUEST

RESETS I2C3SNS WRITE FLAG

HALTS EXECUTION

RESUMES EXECUTION

SERVICES I2C3SNS INTERRUPT

READS I2C3SNS STATUS REGISTER

DELAYS WHILE CPU

COMPLETES WORD WRITE

SETS BUSYW IN CONTROL -

WORD MODE?

HOST

ST7 CPU

ST7 I2C3SNS

Repeat

RAM start address depends on slave address

Byte-Pair Coherency ensured by setting Word Mode

NORMAL EXECUTION

Max

1 Cycle

WRITES ONE BYTE TO RAM

Max

1 Cycle

ISSUES INTERRUPT

ENABLES I2C3SNS

UPDATES CONTROL REGISTER

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