ST72340 datasheet(140/191 Pages) STMICROELECTRONICS

140 / 191 page

ST72340, ST72344, ST72345

140/191

I2C3S INTERFACE (Cont’d)

I2C SLAVE 3 ADDRESS REGISTER

(I2C3SSAR3)

Read / Write

Reset Value: 0000 0000 (00h)

Bit 7:1 = ADDR[7:1] Address of Slave 3

This register contains the first 7 bits of Slave 3 ad-

dress (excluding the LSB) and is user programma-

ble. It is also cleared by hardware when interface

is disabled (PE =0).

Bit 0= EN3 Enable bit for Slave Address 3

This bit is used to enable/disable Slave Address 3.

It is also cleared by hardware when interface is

disabled (PE =0).

0: Slave Address 3 disabled

1: Slave Address 3 enabled

I2C SLAVE 1 MEMORY CURRENT ADDRESS

Read only

Reset Value: 0000 0000 (00h)

Bit 7:0 = CA[7:0] Current address of Slave 1 buffer

This register contains the 8 bit offset of Slave Ad-

dress 1 reserved area in RAM. It is also cleared by

hardware when interface is disabled (PE =0).

I2C SLAVE 2 MEMORY CURRENT ADDRESS

Read only

Reset Value: 0000 0000 (00h)

Bit 7:0 = CA[7:0] Current address of Slave 2 buffer

This register contains the 8-bit offset of Slave Ad-

dress 2 reserved area in RAM. It is also cleared by

hardware when interface is disabled (PE =0).

I2C SLAVE 3 MEMORY CURRENT ADDRESS

Read only

Reset Value: 0000 0000 (00h)

Bit 6:0 = CA[6:0] Current address of Slave 3 buffer

This register contains the 8-bit offset of slave ad-

dress 3 reserved area in RAM. It is also cleared by

hardware when interface is disabled (PE =0).

Note: Slave address 3 can store only 128 bytes.

For slave address 3, CA7 bit will remain 0. i.e. if

the Byte Address sent is 0x80 then the Current Ad-

dress register will hold the value 0x00 due to an

overflow.

ADDR

EN3

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

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