MCP6071 datasheet(14/42 Pages) MICROCHIP

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MCP6071/2/4

DS20002142C-page 14

 2009-2021 Microchip Technology Inc. and its subsidiaries

4.0

APPLICATION INFORMATION

The MCP6071/2/4 family of op amps is manufactured

using Microchip’s state-of-the-art CMOS process and

is specifically designed for low-power, high precision

applications.

4.1

Rail-to-Rail Input

4.1.1

PHASE REVERSAL

The MCP6071/2/4 op amps are designed to prevent

phase reversal when the input pins exceed the supply

voltages. Figure 2-34 shows the input voltage

exceeding the supply voltage without any phase

reversal.

4.1.2

INPUT VOLTAGE LIMITS

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the voltages at

the input pins (see Section 1.1, Absolute Maximum

Ratings †).

The ESD protection on the inputs can be depicted as

shown in Figure 4-1. This structure was chosen to

protect the input transistors and to minimize input bias

current (IB).

FIGURE 4-1:

Simplified Analog Input ESD

Structures.

The input ESD diodes clamp the inputs when they try

to go more than one diode drop below VSS. They also

clamp any voltages that go well above VDD; their break-

down voltage is high enough to allow normal operation,

but not low enough to protect against slow over-voltage

(beyond VDD) events. Very fast ESD events (that meet

the spec) are limited so that damage does not occur.

In some applications, it may be necessary to prevent

excessive voltages from reaching the op amp inputs.

Figure 4-2 shows one approach to protecting these

inputs.

FIGURE 4-2:

Protecting the Analog

Inputs.

A significant amount of current can flow out of the

inputs when the Common Mode voltage (VCM) is below

ground (VSS). See Figure 2-36.

4.1.3

INPUT CURRENT LIMITS

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the voltages at

the input pins (see Section 1.1, Absolute Maximum

Ratings †).

Figure 4-3 shows one approach to protecting these

inputs. The resistors R1 and R2 limit the possible cur-

rents in or out of the input pins (and the ESD diodes, D1

and D2). The diode currents will go through either VDD

or VSS.

FIGURE 4-3:

Protecting the Analog

Inputs.

4.1.4

NORMAL OPERATION

The input stage of the MCP6071/2/4 op amps use two

differential input stages in parallel. One operates at a

low common mode input voltage (VCM), while the other

operates at a high VCM. With this topology, the device

operates with a VCM up to 300 mV above VDD and

300 mV below VSS. (See Figure 2-13). The input offset

voltage is measured at VCM = VSS –0.3V and

VDD + 0.3V to ensure proper operation.

The transition between the input stages occurs when

VCM is near VDD –1.1V (See Figures 2-4, 2-5 and

Figure 2-6). For the best distortion performance and

gain linearity, with noninverting gains, avoid this region

of operation.

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage

Bond

Pad

VIN–

VDD

MCP607X

VOUT

VDD

min(R1,R2)>

VSS –min (V1,V2)

2mA

min(R1,R2)>

max(V1,V2)–VDD

2mA

MCP607X

VOUT

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