MCP4725 datasheet(13/56 Pages) MICROCHIP

13 / 56 page

 2007-2022 Microchip Technology Inc. and its subsidiaries

DS20002039E-page 13

MCP4725

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

3.1

Analog Output Voltage (VOUT)

VOUT is an analog output voltage from the DAC device.

The DAC output amplifier drives this pin with a range of

VSS to VDD.

3.2

Supply Voltage (VDD or VSS)

VDD is the power supply pin for the device. The voltage

at the VDD pin is used as the supply input as well as the

DAC reference input. The power supply at the VDD pin

should be as clean as possible for good DAC

performance.

This pin requires an appropriate bypass capacitor of

about 0.1 µF (ceramic) to ground. An additional 10 µF

capacitor (tantalum) in parallel is also recommended to

further attenuate high frequency noise present in

application boards. The supply voltage (VDD) must be

maintained in the 2.7V to 5.5V range for specified

operation.

VSS is the ground pin and the current return path of the

device. The VSS pin must be connected to a ground

plane through a low impedance connection. If an

analog ground path is available in the application PCB

(printed circuit board), it is highly recommended that

the VSS pin be tied to the analog ground path or

isolated within an analog ground plane of the circuit

board.

3.3

Serial Data Pin (SDA)

SDA is the serial data pin of the I2C interface. The SDA

pin is used to write or read the DAC register and

EEPROM data. The SDA pin is an open-drain N-chan-

nel driver. Therefore, it needs a pull-up resistor from the

VDD line to the SDA pin. Except for START and STOP

conditions, the data on the SDA pin must be stable

during the high period of the clock. The high or low

state of the SDA pin can only change when the clock

signal on the SCL pin is low. Refer to Section 7.0 “I2C

Serial Interface Communication” for more details of I2C

Serial Interface communication.

3.4

Serial Clock Pin (SCL)

SCL is the serial clock pin of the I2C interface. The

MCP4725 acts only as a slave and the SCL pin accepts

only external serial clocks. The input data from the

Master device is shifted into the SDA pin on the rising

edges of the SCL clock and output from the MCP4725

occurs at the falling edges of the SCL clock. The SCL

pin is an open-drain N-channel driver. Therefore, it

needs a pull-up resistor from the VDD line to the SCL

pin.

Refer

Section 7.0

“I2C Serial Interface

Communication” for more details of I2C Serial Interface

communication.

3.5

Device Address Selection Pin (A0)

This pin is used to select the A0 address bit by the user.

The user can tie this pin to VSS (logic ‘0’), or VDD

(logic ‘1’), or can be actively driven by the digital logic

levels, such as the I2C Master Output. See Section 7.2

“Device Addressing” for more details of the address

bits.

TABLE 3-1:

PIN FUNCTION TABLE

MCP4725

Name

Description

SOT-23

DFN

VOUT

Analog Output Voltage

VSS

Ground Reference

VDD

Supply Voltage

SDA

I2C Serial Data

SCL

I2C Serial Clock Input

I2C Address Bit Selection pin (A0 bit). This pin can be tied to VSS or VDD,

or can be actively driven by the digital logic levels. The logic state of this

pin determines what the A0 bit of the I2C address bits should be.

—

Exposed Pad (Note 1)

Note 1: The DFN package has a contact on the bottom of the package. This contact is conductively connected to

the die substrate, and therefore should be unconnected or connected to the same ground as the device’s

VSS pin.

MCP4725 датащи(PDF) 13 Page - Microchip Technology

MCP4725 датащи(HTML) 13 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

датащи скачать

ссылки URL