CS5016 datasheet(14/46 Pages) CIRRUS

14 / 46 page

Asynchronous Sampling

The CS5012A/14/16 internally operate from a

clock which is delayed and divided down from

CLKIN (fCLK/4). If sampling is not synchronized

to this internal clock, the conversion cycle may

not begin until up to four clock cycles after

HOLD goes low even though the charge is

trapped immediately. In this asynchronous mode

(Figure 3a), the four clock cycles add to the mini-

mum 49, 57 and 65 clock cycles (for the

CS5012A/14/16 respectively) to define the maxi-

mum conversion time (see Figure 5a and

Table 1).

Synchronous Sampling

To achieve maximum throughput, sampling can

be synchronized with the internal conversion

clock by connecting the End-of-Track (EOT) out-

put to HOLD (Figure 3b). The EOT output falls

15 CLKIN cycles after EOC indicating the ana-

log

input

has

been

acquired

the

CS5012A/14/16’s specified accuracy. The EOT

output is synchronized to the internal conversion

clock, so the four clock cycle synchronization un-

certainty is removed yielding throughput at

[1/64]fCLK for the CS5012A, [1/72]fCLK for

CS5014 and [1/80]fCLK for CS5016 where fCLK

is the CLKIN frequency (see Figure 5b and Ta-

ble 1).

Conversion

(49 + N cycles)

1 / Throughput

(64 + N cycles)

Output

EOT

Output

EOC

Input

HOLD

Acquisition

(15 cycles)

* Dashed line: CS & RD = 0

CS5012A N = 0

Solid line: See Figure 9

CS5014

N = 8

CS5016

N = 16

Figure 5b. Synchronous (Loopback Mode)

Conversion

Synchronization Uncertainty (4 cycles)

Input

Output

Acquisition

HOLD

EOC

EOT

1 / Throughput

Figure 5a. Asynchronous Sampling (External Clock)

Throughput Time

Conversion Time

Sampling Mode

Synchronous (Loopback)

Asynchronous

Min

64 t clk

N/A

Max

64 t clk

1.32

µs

t clk+

2.25

µs

t clk+

Max

235 ns

53 t clk

49 t clk

235 ns

53 t clk

Min

49 t clk

-7

-12,-24

CS5012A

CS5014

57 t clk

235 ns

61 t clk

57 t clk

72 t clk

N/A

72 t clk

2.25

µs

t clk+

Synchronous (Loopback)

Asynchronous

65 t clk

235 ns

69 t clk

65 t clk

80 t clk

N/A

80 t clk

2.25

µs

t clk+

Synchronous (Loopback)

Asynchronous

CS5016

Table 1. Conversion and Throughput Times (tclk = Master Clock Period)

CS5012A, CS5014, CS5016

2-20

DS14F6

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