LXT6155LE datasheet(38/50 Pages) INTEL

38 / 50 page

LXT6155 — 155 Mbps SDH/SONET/ATM Transceiver

Datasheet

Figure 18. Transmit Parallel Input Data Timing (See Table 28)

Figure 19. Transmit Serial Input Data Timing (See Table 28)

Table 28. Transmit Timing Characteristics (See Figures 18 and 19)

Parameter

Sym

Min

Typ1

Max

Unit

Test Conditions

Transmit serial input clock frequency

155.52

MHz

Transmit serial input clock frequency error

-20

+20

ppm

Compliant with GR253

Transmit serial input clock duty cycle

Transmit serial input clock and data rise /fall

time

1.2

20% - 80%

Transmit parallel input clock frequency

19.44

MHz

Transmit parallel input clock frequency error

-20

+20

ppm

Transmit parallel input clock duty cycle

Transmit parallel input data & clock rise/fall

time2

210

TPICLK to TPID<0:7> hold time

Thtpid

TPICLK to TPID<0:7> setup time

Tstpid

TSICLKP(TSICLKN) to TPOS (TNEG) setup

time

Tstpos

1.25

TSICLKP (TSICLKN) to TPOS (TNEG) hold

time

Thtpos

0.75

1. Typical values are at 25C and 3.3V. They are for design aid only; not guaranteed and not subject to production testing.

2. Not production tested, guaranteed by design and other correlation factors.

Thtpid

TPICLK*

TPID<0:7>

Tstpid

*HW mode timing shown. In SW mode (HWSEL=1) TPICLK polarity can be inverted. See Table 8 for details.

Thtpos

TSICLKP

TPOS

TNEG

Tstpos

TSICLKN

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