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PIN CONFIGURATIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

16

15

DGND

DAC8802

(TOP VIEW)

LDAC

MSB

RS

CS

CLK

SDI

DAC8802

SBAS351A – AUGUST 2005 – REVISED DECEMBER 2005

PIN DESCRIPTION

PIN

NAME

DESCRIPTION

1

Establish voltage output for DAC A by connecting to external amplifier output.

DAC A Reference voltage input terminal. Establishes DAC A full-scale output voltage.

2

3

DAC A Current output.

4

DAC A Analog ground.

5

DAC B Analog ground.

6

DAC B Current output.

DAC B Reference voltage input terminal. Establishes DAC B full-scale output voltage.

7

8

Establish voltage output for DAC B by connecting to external amplifier output.

9

SDI

Serial data input; data loads directly into the shift register.

Reset pin; active low input. Input registers and DAC registers are set to all 0s or midscale.

10

RS

Register data = 0x0000 when MSB = 0. Register data = 0x2000 when MSB = 1 for

DAC8802.

Chip-select; active low input. Disables shift register loading when high. Transfers serial

11

CS

register data to input register when CS/LDAC goes high. Does not affect LDAC operation.

12

DGND

Digital ground.

13

Positive power-supply input. Specified range of operation is 2.7 V to 5.5 V.

MSB bit sets output to either 0 or midscale during a RESET pulse (RS) or at system

14

MSB

power-on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB

Load DAC register strobe; level sensitive active low. Transfers all input register data to

15

LDAC

the DAC registers. Asynchronous active low input. See Table 2 for operation.

16

CLK

Clock input. Positive edge clocks data into shift register.

5