The information in this document is subject to change without notice.

BIPOLAR ANALOG INTEGRATED CIRCUIT

µµµµPC4093

J-FET INPUT LOW-OFFSET OPERATIONAL AMPLIFIER

Document No. G13906EJ1V0DS00 (1st edition)

Date Published December 1998 N CP(K)

Printed in Japan

DATA SHEET

©

1998

The

µPC4093 operational amplifier is a high-speed version of the µPC4091. NEC's unique high-speed PNP

transistor (fT = 300 MHz) in the output stage realizes a high slew rate of 25 V/

µs under voltage-follower conditions

without an oscillation problem. Zener-zap resistor trimming in the input stage produces excellent offset voltage and

temperature drift characteristics.

With AC performance characteristics that are two times better than conventional bi-FET operation amplifiers, the

µPC4093 is ideal for fast integrators, active filters, and other high-speed circuit applications.

FEATURES

•

Stable operation with 220 pF capacitive load

•

Low input offset voltage and offset voltage null

capability

±2.5 mV (MAX.)

±7

µV/°C (TYP.) temperature drift

•

Very low input bias and offset currents

•

Low noise : en = 19 nV/

√Hz (TYP.)

•

Output short circuit protection

•

High input impedance ... J-FET Input Stage

•

Internal frequency compensation

•

High slew rate: 25 V/

µs (TYP.)

ORDERING INFORMATION

Part Number

Package

µPC4093C

8-pin plastic DIP (300 mil)

µPC4093G2

8-pin plastic SOP (225 mil)

EQUIVALENT CIRCUIT

PIN CONFIGURATION

(Top View)

II

IN

Q1

Q2

Q4

Q5

Q8

D1

C1

Q10

V+

V –

OUT

Q9

Q7

Q6

Q3

OFFSET

NULL

OFFSET

NULL

TRIMMED

(1)

(5)

(3)

(2)

(7)

(4)

(6)

HIGH SPEED

PNP

PC4093C, 4093G2

1

2

3

4

8

7

6

5

NC

V+

OUT

OFFSET

NULL

+

−

OFFSET

NULL

NC : No Connection

Remark

II

IN

µ

V

−