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BIPOLAR ANALOG INTEGRATED CIRCUIT

µPC4092

J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER

Document No. G13905EJ2V0DS00 (2nd edition)

Date Published March 2004 N CP(K)

Printed in Japan

DATA SHEET

The mark

shows major revised points.

c

The

µPC4092 dual operational amplifier offers high input impedance, low offset voltage, high slew rate, and stable

AC operating characteristics. NEC's unique high-speed PNP transistor (fT = 300 MHz) in the output stage solves the

oscillation problem of current sinking with a large capacitive load. Zener-zap resistor trimming in the input stage

produces excellent offset voltage and temperature drift characteristics.

FEATURES

•

Stable operation with 10000 pF capacitive load

•

Low input offset voltage

±3 mV (MAX.)

±7

µV/°C (TYP.) temperature drift

•

Very low input bias and offset currents

•

Low noise : en = 19 nV/

√Hz (TYP.)

•

Output short circuit protection

•

High input impedance ... J-FET Input Stage

•

Internal frequency compensation

•

High slew rate: 15 V/

µs (TYP.)

ORDERING INFORMATION

Part Number

Package

µPC4092C

8-pin plastic DIP (7.62 mm (300))

µPC4092G2

8-pin plastic SOP (5.72 mm (225))

EQUIVALENT CIRCUIT (1/2 Circuit)

PIN CONFIGURATION

(Top View)

II

IN

Q1

Q2

Q4

Q5

Q8

D1

C1

Q10

V

+

V

−

OUT

Q9

Q7

Q6

Q3

TRIMMED

HIGH SPEED

PNP









PC4092C, 4092G2

1

1

2

3

4

8

7

6

5

V

+

OUT2

II2

IN2

+

−

II1

IN1

OUT1

V

−

2

−

+

µ