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MPC8560 датащи(PDF) 70 Page - Freescale Semiconductor, Inc

номер детали MPC8560
подробное описание детали  Integrated Processor Hardware Specifications
PDF  108 Pages
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производитель  FREESCALE [Freescale Semiconductor, Inc]
домашняя страница  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8560 датащи(HTML) 70 Page - Freescale Semiconductor, Inc

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MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
70
Freescale Semiconductor
RapidIO
eye pattern to change from one that complies with the RapidIO receive mask to one that does not comply with the
mask. The data carried by any given data signal in the interface may not be correlated with the data carried by any
other data signal in the interface. The zero-crossings of the clock associated with a data signal shall be used as the
timing reference for aligning the multiple recordings of the data signal when the recordings are overlaid.
While the method used to make the recordings and overlay them to form the eye pattern is not specified, the method
used shall be demonstrably equivalent to the following method. The signal under test is repeatedly recorded with a
digital oscilloscope in infinite persistence mode. Each recording is triggered by a zero-crossing of the clock
associated with the data signal under test. Roughly half of the recordings are triggered by positive-going clock
zero-crossings and roughly half are triggered by negative-going clock zero-crossings. Each recording is at least 1.9
UI in length (to ensure that at least one complete eye is formed) and begins 0.5 UI before the trigger point (0.5 UI
before the associated clock zero-crossing). Depending on the length of the individual recordings used to generate
the eye pattern, one or more complete eyes will be formed. Regardless of the number of eyes, the eye whose center
is immediately to the right of the trigger point is the eye used for compliance testing.
An example of an eye pattern generated using the above method with recordings 3 UI in length is shown in
Figure 47. In this example, there is no skew between the signal under test and the associated clock used to trigger
the recordings. If skew was present, the eye pattern would be shifted to the left or right relative to the oscilloscope
trigger point.
Figure 47. Example Receiver Input Eye Pattern
Figure 48 shows the definitions of the data to clock static skew parameter tSKEW,PAIR and the data valid window
parameter DV. The data and frame bits are those that are associated with the clock. The figure applies for all
zero-crossings of the clock. All of the signals are differential signals. VD represents VOD for the transmitter and VID
for the receiver. The center of the eye is defined as the midpoint of the region in which the magnitude of the signal
voltage is greater than or equal to the minimum DV voltage.
0
+
0.5 UI
1.0 UI
1.0 UI
Oscilloscope
(Recording)
Trigger Point
Eye Pattern
Eye Used for
Compliance
Testing



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