KT133A - VT8363A
Preliminary Revision 0.1, October 9, 2000
-15-
Pin Descriptions
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Test Functions
Signal Name
Pin #
I/O
Signal Description
TESTIN
H23
I
PLL Test Input. Normally connected to VCC3.
Clock / Reset Control
Signal Name
Pin #
I/O
Signal Description
HCLK
G22
I
Host Clock. This pin receives the host CPU clock (66 / 100 / 133 MHz). This clock
is used by all VT8363A logic that is in the host CPU domain. The memory interface
logic will also use this clock if selected (memory system timing can alternately be
selected to use the AGP bus clock). The CPU clock must lead the AGP clock by 0.2
± 0.5 nsec.
PCLK
AA5
I
PCI Clock. This pin receives a buffered host clock divided-by-6 to create 33 MHz.
This clock is used by all of the VT8363A logic that is in the PCI clock domain. This
clock input must be 33 MHz maximum to comply with PCI specification
requirements and must be synchronous with the host CPU clock, HCLK. The host
CPU clock must lead the PCI clock by 1.5 ± 0.5 nsec.
GCLK
AB14
O
AGP Clock. This pin drives the AGP bus clock (66 MHz). This clock is used by all
VT8363A logic that is in the AGP clock domain. The AGP clock is synchronous to
the 200 MHz host CPU clock.
GCLKF
AC15
I
AGP Clock Feedback. Connect to GCLK.
MCLK
R22
O
DRAM Clock. Output from internal clock generator to the external clock buffer.
MCLKF
P23
I
DRAM Clock Feedback. Input from MCLK via the external clock buffer.
RESET#
AB5
I
Reset. Input from south bridge chip. When asserted, this signal resets the VT8363A
and sets all register bits to the default value. The rising edge of this signal is used to
sample all power-up strap options
PWROK
AC19
I
Power OK.
SUSST#
AB19
I
Suspend Status. For implementation of the Suspend-to-DRAM feature. Connect to
an external pullup to disable.
Figure 3. CPU / SDRAM / AGP / PCI Clock Connections
“Zero
Delay”
Clock
Buffer
VT8363A
North Bridge
AGP
Slot
MCLKO
MCLKF
GCLKF
GCLKO
To
SDRAMs
Athlon
CPU
Clock
Generator
PCI
Slots
HCLK
PCLK
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