Nexperia

74HC20

Dual 4-input NAND gate

4. Functional diagram

1A

1B

1C

1D

1

2

4

6

1Y

5

2A

2B

2C

2D

9

10

12

8

2Y

13

aaa-004014

Fig. 1. Functional diagram

1A

1B

1C

1D

1

2

4

6

1Y

5

2A

2B

2C

2D

9

10

12

8

2Y

13

aaa-004015

Fig. 2. Logic symbol

&

6

1

2

4

5

&

8

9

10

12

13

aaa-004016

Fig. 3. IEC Logic symbol

A

B

C

D

Y

aaa-004017

Fig. 4. Logic diagram

5. Pinning information

5.1. Pinning

VCC

2D

2C

n.c.

2B

2A

2Y

1

2

3

4

5

6

7

8

10

9

12

11

14

13

74HC20

aaa-004018

1A

1B

n.c.

1C

1D

1Y

GND

Fig. 5. Pin configuration SOT108-1 (SO14)

1A

VCC

1B

2D

n.c.

2C

1C

n.c.

1D

2B

1Y

2A

GND

2Y

1

2

3

4

5

6

7

8

10

9

12

11

14

13

74HC20

aaa-004019

Fig. 6. Pin configuration SOT402-1 (TSSOP14)

74HC20

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 6 — 5 February 2021

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