Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
13
1.5.1 Example Part Numbers
Part
Manufacturer
Part Number
Website
30 MHz Fundamental
Crystal (Y1)
KDS
AT-49 30.000-16
http://www.kdsj.co.jp/english.html
Ferrite Beads (L1-L2)
Taiyo Yuden
FBMJ2125HS420-T
http://www.t-yuden.com/ferritebeads/index.cfm
1
µH Inductor, 10%, 0805
Pkg (L3-L4)
Taiyo Yuden
LK21251R0K
http://www.t-yuden.com/inductors/index.cfm
2.43K, 1% resistor, 0.1
Watt, 0603 Pkg
(R5)
Panasonic
ERJ6ENF2431V
http://www.panasonic.com/industrial/compone
nts/pdf/002_er13_erj_2r_3r_6r_3e_6e_8e_14_
12_dne.pdf
USB B Connector
Newnex
URB-1001
http://www.newnex.com
Note that the crystal should have a tolerance of +/- 0.005% (50 ppm) to guarantee a data rate of 480 Mbps +/- 500
ppm.
1.5.2
General PCB Layout Guidelines
USB2.0 high-speed 480 Mbits/sec data transfers utilize 400 mV differential signaling. This requires special Printed
Circuit Board layout requirements. Intel provides some USB layout guidelines in the following document:
http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf. In addition, NetChip provides the following guidelines:
The following guidelines must be followed to insure proper operation of the NET2272. It is
strongly suggested that schematics and PCB layout be submitted to support@netchip.com
for review prior to PCB fabrication.
1.5.2.1 USB Differential Signals
•
Consult with board manufacturer for determining layer separation, trace width, and trace separation for
maintaining differential impedance of 90 ohms.
•
Maintain equal trace lengths for D+ and D-.
•
Minimize number of vias and curves on D+ and D- traces.
•
Use two 45 degree turns instead of one 90 degree turn.
•
Minimize trace lengths shown in bold in the schematic in section 1.5.
•
Prevent D+ and D- traces from crossing a power plane void. The same ground layer shall be kept next to
the D+ and D- traces.
•
Digital Ground (VSS) layer should be placed next to the layer where D+ and D- are routed.
•
Avoid using studs or test points for observing USB signals.
•
Maximize the distance of D+ and D- from other signals to prevent crosstalk.
1.5.2.2 Analog VDD (power)
•
Analog power must be filtered from the digital power using the recommended circuit provided.
•
Analog VDD and digital VDD must be connected via 1
µH inductor.
•
Analog VDD must be separated from digital VDD. If analog VDD and digital VDD are in the same layer,
split the layer to accommodate the two power signals.
•
AVDD and PVDD pins should be connected to analog VDD.
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