FireLink USB
82C862
912-2000-030
Page 23
Revision: 1.0
®
5.0
Register Descriptions
The 82C862 has three types of register spaces:
1.
PCI Configuration Register Space
2.
Host Controller Register Space
3.
I/O Register Space
The subsections that follow detail the locations and access mechanisms for the registers located within these register spaces.
Notes: 1. All bits/registers are read/write and their default value is 0 unless otherwise specified.
2. All reserved bits/registers MUST be written to 0 unless otherwise specified.
5.1
PCICFG Register Space
The FireLink USB 82C862 part is a multi-function PCI device.
Function 0: Primary USB host controller module
Function 1: Secondary USB host controller module.
The two USB controller modules each have their own PCI configuration space. The configuration space of both USB
controllers are similar except for the value in the Interrupt Pin register (PCICFG 3Dh) and the Interrupt Pin Selection register
(PCICFG 4Ch), because the controllers are assigned different interrupt pins by default.
The configuration space of each PCI USB controller module is referred to as PCICFG. The bit formats for these registers are
described in Section 5.1.2.
5.1.1
Programming Differences from 82C861 Component
While the physical device part number of this chip is 82C862, the USB controller modules identify themselves as 82C861 to
maintain backward software compatibility with the previous OPTi chip. Software can differentiate between the chips by reading
the Revision ID of 20h in PCICFG 08h (previous revisions read back 10h or lower).
Additional revision 20h changes that relate to the programming interface are as follows.
• The 82C862 component adds PCI power management, reflected in changes in PCICFG 06h and the addition of PCICFG
34h, 4Dh, and F0-F5h.
• The 82C862 part provides a way to restore the Subsystem Vendor ID and Subsystem ID values in a single-step process,
necessary for proper context restoration after the chip is powered down during OS Suspend operations. This new approach
is reflected in the deletion of PCICFG 50h[3] and the addition of PCICFG 7C-7Fh.
• The specific I2C pins of the 82C861 part have been replaced by general purpose I/O pins, resulting in the deletion of
PCICFG 4Eh.
• The IRQ Driveback feature is no longer supported, resulting in the deletion of PCICFG 51h and 54-57h.
• Changes to the chip pinout result in major changes to the PCICFG 52h bit definitions.
• PCICFG 4Ch has been added to allow both USB controller modules to share a single PCI interrupt.
• All bits of MEMOFST 4Bh are now read/writeable (previous chip versions allowed only bits [1:0] to be written).
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