Nexperia

74LVC823A

9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

5. Pinning information

5.1. Pinning

74LVC823A

OE

VCC

D0

Q0

D1

Q1

D2

Q2

D3

Q3

D4

Q4

D5

Q5

D6

Q6

D7

Q7

D8

Q8

MR

CE

GND

CP

001aaa845

1

2

3

4

5

6

7

8

9

10

11

12

14

13

16

15

18

17

20

19

22

21

24

23

Fig. 5. Pin configuration SO24 (SOT137-1) and

TSSOP24 (SOT355-1)

001aaa846

74LVC823A

Transparent top view

CE

D8

MR

Q8

D7

Q7

D6

Q6

D5

Q5

D4

Q4

D3

Q3

D2

Q2

D1

Q1

D0

Q0

11

14

10

15

9

16

8

17

7

18

6

19

5

20

4

21

3

22

2

23

terminal 1

index area

GND(1)

(1) This is not a ground pin. There is no electrical or

mechanical requirement to solder the pad. In case

soldered, the solder land should remain floating or

connected to GND.

Fig. 6. Pin configuration SOT815-1 (DHVQFN24)

5.2. Pin description

Table 2. Pin description

Pin

Name

Description

OE

1

output enable input (active LOW)

MR

11

master reset input (active LOW)

D0, D1, D2, D3, D4, D5, D6, D7, D8

2, 3, 4, 5, 6, 7, 8, 9, 10

data input

Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8

23, 22, 21, 20, 19, 18, 17, 16, 15

3-state flip-flop output

CP

13

clock input (LOW to HIGH;

edge-triggered)

CE

14

clock enable input (active LOW)

GND

12

ground (0 V)

VCC

24

supply voltage

74LVC823A

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© Nexperia B.V. 2020. All rights reserved

Product data sheet

Rev. 6 — 18 June 2020

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