SC1100 datasheet(13/348 Pages) NSC

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Architecture Overview (Continued)

1.1.7.3

Slave PCI Burst Length Control

The name of this bit differs from that described in the GX1

Processor Series datasheet. There, it is called SDBE. Oth-

erwise, the functionality is the same as the standalone GX1

processor, See Table 1-2.

1.1.7.4

Scratchpad Size Control

The GX1 Processor Series datasheet allows additional

sizes of 3 KB and 4 KB, which are disallowed in the

SC1100, see Table 1-3.

1.1.7.5

Disable Virtual VGA

The registers detailed in Table 1-4 must be set as indicated

in order for the SC1100 to function properly.

1.1.7.6

Disable Display Controller

In order for the SC1100 to function correctly, the Display

Controller

Configuration

and

Status

registers

(GX_BASE+Offset 8300h-830Fh) must all be set with 0s.

Table 1-2. Slave PCI Burst Length Control

Bit

Description

Index 41h

PCI Control Function 2 Register (R/W)

Reset Value: 96h

Width: Byte

Slave Disconnect Boundary Enable (SDBE1): GX1 as a PCI slave:

Works in conjunction with bit 0 of the MCR register. For details see Section 3.2 on page 50.

Note:

When Slave Disconnect Boundary is disabled for Write, the cache should use Write Through Mode instead of

Write Back Mode. The Write Through Mode implies some overall performance degradation since all Writes go to

Memory. If the Write back Mode is used in this case, the cache coherency cannot be guaranteed.

Table 1-3. Scratchpad Size Control

Bit

Description

Index B8h

Graphics Control Register (R/W)

Reset Value: 00h

Width: Byte

3:2

Scratchpad Size: Specifies the size of the scratchpad cache. Either a 0 KB or a 2 KB Scratchpad Size must be chosen.

For details, see the GX1 Processor Series datasheet.

Table 1-4. Disable Virtual VGA

Bit

Description

Index 20h

PCR0: Performance Control 0 Register (R/W)

Reset Value: 07h

Width: Byte

VGA Memory Write SMI Generation (VGAMWSI). Must be set to 0.

Index B9h

VGACTL Register (R/W)

Reset Value: 00h

Width: Byte

SMI generation for VGA memory range B8000h to BFFFFh. Must be set to 0.

SMI generation for VGA memory range B0000h to B7FFFh. Must be set to 0.

SMI generation for VGA memory range A0000h to AFFFFh. Must be set to 0.

Index BAh-BDh

VGAM Register (R/W)

Reset Value: xxxxxxxxh

Width: DWORD

31:0

SMI generation for address range A0000h to AFFFFh. Must be set to all 0s.

Gx Based + Offset 8004h - 8007h

BC_XMAP_1 Register (R/W)

Reset Value: 00000000h

Width: DWORD

Graphics Enable for B8 Region (GEB8). Must be set to 0.

Graphics Enable for B0 Region (GEB0). Must be set to 0.

SMID: All I/O accesses for address range 3D0h to 3DFh generate an SMI. Must be set to 0.

SMIC: All I/O accesses for address range 3C0h to 3CFh generate an SMI. Must be set to 0.

SMIB: All I/O accesses for address range 3B0h to 3BFh generate an SMI. Must be set to 0.

Graphics Enable for A Region (GEA). Must be set to 0.

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