LTC9101-2 datasheet(23/34 Pages) AD

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Data Sheet

LTC9101-2A/LTC9102

APPLICATIONS INFORMATION

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Rev. 0 | 23 of 34

tCUT timer duration are programmable. Refer to the LTC9101-2A

software interface data sheet for encoding details.

Current Limit

Each LTC9101-2A/LTC9102 port includes an implicit current limiting

threshold (ILIM-2P), with a corresponding timer (tLIM). The ILIM thresh-

old is a function of the applied "Police" threshold, as shown in Table

11.

Table 11. ILIM Values

Police

ILIM (Typical)

≤320mA

425mA1

>320mA

850mA

1 PDs powered on as "Class 4" devices (that is, 2-event classification) maintain

an 850mA ILIM threshold regardless of the "Police" setting.

The LTC9101-2A/LTC9102 actively controls the MOSFET gate

drive to keep the port current below ILIM. Figure 7 shows that the

LTC9101-2A/LTC9102 ILIM threshold is implemented as a two-stage

foldback circuit that reduces the port current if the port voltage falls

below the normal operating voltage. This keeps MOSFET power

dissipation at safe levels. The ILIM current limiting circuit is always

enabled and actively limiting port current.

The tLIM timer duration is adjustable, as shown in Table 12. Each

quad offers an independent timer duration control. The tLIM timer

duration may be adjusted at any time. The updated timer duration is

immediately applied to all ports in the affected quad.

Table 12. TLIM Settings

Field

TLIM (Typical)

00b (Default)

Type 1 TLIM 60ms

01b

Spare TLIM 17ms

10b

Type 2 TLIM 13ms

11b

Spare TLIM 11ms

MOSFET Fault Detection

LTC9101-2A/LTC9102 PSE ports are designed to tolerate signifi-

cant levels of abuse, but in extreme cases it is possible for an

external MOSFET to be damaged. A failed MOSFET may short

source to drain, which makes the port appear to be on when it

should be off; this condition may also cause the sense resistor to

fuse open, turning off the port but causing SENSE to rise to an

abnormally high voltage. A failed MOSFET may also short from

gate to drain, causing GATE to rise to an abnormally high voltage.

OUT, SENSE, and GATE are designed to tolerate up to 80V faults

without damage.

If the LTC9101-2A/LTC9102 detects any of these conditions for

more than 3.8ms, it disables all port functionality, reduces the gate

drive pull-down current for the port, and reports a "MOSFET Fault"

detection status. This is typically a permanent fault, but the host

can attempt to recover by resetting the port, setting the port to

shutdown mode, or by resetting the entire chip if a port reset fails

to clear the fault. If the MOSFET is in fact bad, the fault quickly

returns, and the port disables itself again. The remaining ports of

the LTC9101-2A/LTC9102 are unaffected.

An open or missing MOSFET does not trigger a "MOSFET Fault"

detection status, but causes a tSTART fault if the LTC9101-2A/

LTC9102 attempts to turn on the port.

Disconnect

The LTC9101-2A/LTC9102 monitors powered ports to ensure the

PD continues to draw the minimum specified current. The IHOLD

threshold, monitored as the VHOLD threshold across the 0.1Ω sense

resistor, is used to determine if a PD is disconnected.

A disconnect timer (tDIS) counts up whenever the port current is

below the IHOLD threshold, indicating that the PD is disconnected. If

the tDIS timer expires, the port is turned off and the corresponding

disconnect fault is set. Alternatively, if the current increases above

IHOLD for a duration greater than tMPS before the tDIS timer expires,

the tDIS timer resets and the PD remains powered.

Although not recommended, the DC disconnect feature can be

disabled by clearing the corresponding "DC Disconnect Enable"

bit. Disabling the DC disconnect feature forces the LTC9101-2A/

LTC9102 out of compliance with the IEEE standard. A powered port

stays powered after the PD is removed; the still-powered port may

be subsequently connected to a non-PoE data device, potentially

causing damage.

The LTC9101-2A/LTC9102 does not include AC disconnect circui-

try.

Fast Surge Recovery

High reliability systems demand excellent surge recovery. It is

increasingly important for a PSE to minimize power disruption to

the PDs during extreme power transients. Furthermore, PDs that do

not meet minimum bulk capacitance requirements are particularly

vulnerable to power brownouts with traditional PSE solutions. The

LTC9101-2A/LTC9102 provides an improved hot swap responsive-

ness with excellent recovery from surge events.

During a surge event, the LTC9102 GATE pin quickly turns off the

external MOSFET current flow to protect the PSE, the MOSFET,

and downstream circuitry. As the surge dissipates, the LTC9102

quickly turns the MOSFET back on in a safe, current limited man-

ner, while minimizing power disruption to the PD. The LTC9102

fast MOSFET turn off and power recovery better support both

IEEE compliant PDs and PDs with lower bulk capacitance in high

reliability applications.

Port Current Readback

The LTC9101-2A measures the current through each port with

per-port A/D converters. Note that port current is only valid when

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