Nexperia

74HC03; 74HCT03

Quad 2-input NAND gate; open-drain output

4. Functional diagram

mna212

1A

1Y

1B

1

2

3

2A

2Y

2B

4

5

6

3A

3Y

3B

9

10

8

4A

4Y

4B

12

13

11

Fig. 1. Logic symbol

aaa-008083

3

1

2

&

6

4

5

&

8

9

10

&

11

12

13

&

Fig. 2. IEC logic symbol

001aab715

Y

GND

A

B

Fig. 3. Logic diagram (one gate)

5. Pinning information

5.1. Pinning

74HC03

74HCT03

1A

VCC

1B

4B

1Y

4A

2A

4Y

2B

3B

2Y

3A

GND

3Y

aaa-008084

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 4. Pin configuration SOT108-1 (SO14)

74HC03

74HCT03

1A

VCC

1B

4B

1Y

4A

2A

4Y

2B

3B

2Y

3A

GND

3Y

aaa-008085

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 5. Pin configuration SOT402-1 (TSSOP14)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1A to 4A

1, 4, 9, 12

data input

1B to 4B

2, 5, 10, 13

data input

1Y to 4Y

3, 6, 8, 11

data output

GND

7

ground (0 V)

VCC

14

supply voltage

74HC_HCT03

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 6 — 10 August 2021

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