53209-580-00 C
FAS209
1
Features
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Compliance with ANSI SCSI-2 standard
X3.131-1994 and SCSI-1
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Compliance with ANSI X3T10/855D SCSI-3
parallel interface (SPI) standard
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Compliance with ANSI SCSI configured
automatically (SCAM) protocol levels 1 and 2
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Synchronous data transfers up to 10 Mbytes/sec fast
SCSI and 5 Mbytes/sec normal SCSI
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Asynchronous data transfers up to 7 Mbytes/sec
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Up to 12 Mbytes/sec DMA burst transfer rate
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Clock rates up to 40 MHz
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Supports hot plugging
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Programmable active negation
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Low-input capacitance
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Programmable split-bus architecture
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DMA interface options
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Two bus configurations
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On-chip, 48-mA, single-ended drivers and receivers
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Parity pass-through on FIFO data
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Initiator and target roles
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SCSI sequences implemented without
microprocessor intervention
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Part-unique ID code
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Eight-bit, single-ended SCSI operations
Product Description
The FAS209 is a high-performance SCSI interface chip
designed to maximize transfer rates over the SCSI bus. It
is the enhanced SCSI follow-on to QLogic’s FAS216 SCSI
processor chip, adding active negation and SCAM to the
FAS216 design. The FAS209 supports bidirectional,
single-ended SCSI operations. The block diagram of the
FAS209 is illustrated in figure 1.
The FAS209 maximizes transfer rates by sustaining
asynchronous data rates of up to 7 Mbytes/sec and fast,
synchronous data transfer rates of 10 Mbytes/sec. The
normal 5 Mbytes/sec synchronous transfer rate is also
supported. With its on-chip, 48-mA, single-ended drivers
and receivers, the FAS209 can connect directly to the SCSI
bus, minimizing board space requirements. The FAS209’s
highly integrated structure provides users with numerous
benefits.
Initiator and target roles are supported; therefore, the
FAS209 can be used in both host adapter and peripheral
applications. The FAS209 performs such functions as bus
arbitration, selection of a target, or reselection of an
initiator. It handles message, command, status, and data
transfer between the SCSI bus and the chip’s 16-byte
internal FIFO or a buffer memory. The above functions are
internal processes performed by the FAS209 chip without
microprocessor intervention.
SCAM Implementation
The FAS209 supports levels 1 and 2 of the SCAM
protocol. (Refer to the latest revision of X3T10/855D,
Annex B.) The SCAM protocol requires direct access and
control over the SCSI data bus and several of the SCSI
phase and control signals. The majority of the SCAM
protocol can be implemented in firmware at
microprocessor speeds. The following SCAM features are
supported in the hardware:
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Arbitration without an ID
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Slow response to selection with an unconfirmed ID
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Detection of and response to SCAM selection
Bus Configuration
The FAS209 split-bus architecture separates the two
high-traffic information buses of the system, providing
maximum efficiency and throughput. The versatile bus
architecture supports various microprocessor and DMA
bus configurations, including those listed below:
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Microprocessor interface via the PAD bus or the DB
bus
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Concurrent microprocessor and DMA accesses
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PAD bus selectable as a data-only bus
QLogic Corporation
FAS209 Fast Architecture SCSI
Data Sheet
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