52

DS261DB2

CDB61584A

Dual Line Interface Unit

POWER SUPPLY

As shown on the evaluation board schematic in

Figures 1-5, power is supplied to the board from an

external +5 Volt supply connected to the two bind-

ing posts labeled V+ and GND. Zener diode Z1

protects the components on the board from re-

versed supply connections and over-voltage dam-

age.

Capacitor

C16

provides

power

supply

decoupling and ferrite bead L1 helps isolate the

CS61584A and buffer supplies. Both sides of the

evaluation board contain extensive areas of ground

plane to insure optimum performance.

Capacitors C3, C5-C8, C13, C18, and C38 provide

power supply decoupling for the CS61584A. The

BGREF pin is pulled down through resistor R10 to

provide an internal current reference. The buffers

are decoupled using capacitors C9, C15, and C19.

Ferrite beads L2-L4 help reduce the power supply

noise that is coupled from the buffers to the power

supply.

BOARD CONFIGURATION

Slide switch SW6 selects hardware or host mode

operation. Hardware mode is selected when switch

SW6 is in the "HW" position and sets the MODE

pin of the CS61584A to a logic 0. Host mode is se-

lected when switch SW6 is in the "SW" position

and sets the MODE pin of the CS61584A to a

logic 1.

Hardware Mode

In Hardware mode operation, the evaluation board

is configured using DIP switches SW2, SW3, and

SW4. In this mode, the switches establish the digi-

tal control inputs for both line interface channels.

Closing a DIP switch towards the label sets the

CS61584A control pin of the same name to a logic

1. The host processor interface J26 should not be

used in the Hardware mode.

The CDB61584A switches and functions are listed

below:

-

TAOS1, TAOS2: transmit all ones;

-

LLOOP: local loopback of both channels;

-

RLOOP1,2: remote loopback 1,2;

-

PD1, PD2: power down;

-

ATTEN0, ATTEN1: jitter attenuator selection;

-

CLKE: RCLK edge polarity;

-

1XCLK: clock frequency selection;

-

CONx1, CONx2: line configuration settings.

All switch inputs are pulled-down using resistor

networks RP2-RP5.

The LOS1 and LOS2 LED indicators illuminate

when the line interface receiver has detected a loss

of signal. Headers J7 and J13 must be jumpered in

the "TNEG" position to provide connectivity to the

BNC input in Hardware mode.

Host Mode

In Host mode operation, the evaluation board sup-

ports serial-port operation over interface port J26

using the printer port of a host PC equipped with

the enclosed software. The evaluation board is con-

nected to the host PC using the ribbon cable provid-

ed. The SW2 switch position labeled "ATTEN0"

must be open to set the P/S pin of the CS61584A to

a logic 0 and enable serial-port operation.

An external microprocessor may also interface to

the evaluation board for the purposes of system

software development. The CS61584A interrupt

pin is connected to pin 23 of interface port J26 to

facilitate software development. The SW2 switch

position labeled "CLKE/IPOL" establishes the po-

larity of the interrupt pin. If an active low interrupt

is selected (IPOL low), the interrupt pin must be

pulled-up through resistor R55 by placing a jumper

on header J24. The SW2 switch position labeled

"RLOOP1" must be in the open position for proper

operation of the interrupt.

The LOS1 and LOS2 LED indicators illuminate

when the line interface receiver has detected a loss

of signal. If coder mode is enabled in the

CS61584A register set, the AIS alarm condition is