4

DS684DB1

CDB4352

1. CDB4352 SYSTEM OVERVIEW

The CDB4352 evaluation board is an excellent means of quickly evaluating the CS4352. The CS8416 digital audio

interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test

equipment. The evaluation board also allows the user to supply external PCM clocks and data through a header for

system development.

The CDB4352 schematic has been partitioned into five schematics, as shown in Figures 32 through 36. Each par-

titioned schematic is represented in the system diagram shown in Figure 31. Notice that the system diagram also

includes the interconnections between the partitioned schematics.

2. CS4352 DIGITAL-to-ANALOG CONVERTER

A description of the CS4352 is included in the CS4352 datasheet.

3. CS8416 DIGITAL AUDIO RECEIVER

The system receives and decodes the standard S/PDIF data format using a CS8416 Digital Audio Receiver,

Figure 35. The outputs of the CS8416 include a serial bit clock, serial data, left-right clock, and a 128/256 Fs master

clock. The CS8416 data format is fixed to I²S. The operation of the CS8416 and a discussion of the digital audio

interface is included in the CS8416 datasheet.

The evaluation board has been designed such that the input can be either optical or coaxial, see Figure 35. How-

ever, both inputs cannot be driven simultaneously.

Position 2 of S1 sets the output MCLK to LRCK ratio of the CS8416. This switch should be set to 256 (LO) for input

Fs<=48 kHz and can be either 256 (LO) or 128 (HI) for Fs>48 kHz

4. INPUT FOR CLOCKS AND DATA

The evaluation board has been designed to allow interfacing to external systems via the header J13. Header J13

allows the evaluation board to accept externally generated PCM clocks and data. The schematic for the clock/data

input is shown in Figure 34. Switch position 1 of S1 selects the source as either CS8416 or header J13.

Please see the CS4352 datasheet for more information.

5. POWER SUPPLY CIRCUITRY

Power is supplied to the evaluation board by three binding posts (GND, VL, and VA_H), see Figure 36. The VL sup-

ply can be jumpered to a +3.3 V regulator or provided externally through the VL binding post. VD and VA is normally

supplied by the 3.3 V regulator but can be disconnected using J4 and J6 and then have external voltage applied to

the VD and VA test points. The +5 V supply (which powers the regulators for this board) is normally supplied by a

5 V regulator but can be supplied externally by removing J7 and applying 5 V to TP8.

Power consumption of the CS4352 can be measured through the voltage drop at J8, J9, J10, and J11 when the

shunts are removed.

WARNING: Refer to the CS4352 datasheet for maximum allowable voltages levels. Operation outside of this range

can cause permanent damage to the device.