TC236

680-

× 500-PIXEL CCD IMAGE SENSOR

SOCS043A – JUNE 1994 – REVISED NOVEMBER 1994

8

POST OFFICE BOX 655303

Expanded Section of

Parallel Transfer

IAG1, 2

SAG

SRG

1

µs Minimum

684 Pulses

684 Pulses

ODB

IAG1, 2

SAG

SRG

RST

Clear

Integrate

Transfer to Memory

Readout

250 Cycles

500 Pulses

500 Pulses

500 Pulses

Figure 6. Progressive-Scan Timing With Dual Register Readout

serial registers

The storage-area gate and serial gate(s) are used to transfer the charge line by line from the storage area into

the serial register(s). Depending on the readout mode, one or both serial registers is used. If both are used, the

registers are read out in parallel.

readout and video processing

After transfer into the serial register(s), the pixels are read out and placed onto a charge-detection node. The

node must be reset to a reference level before the next pixel is placed onto the detection node. The timing for

the serial-register readout, which includes the external pixel clamp and sample-and-hold signals needed to

implement correlated double sampling, is shown in Figure 7. As the charge is transferred onto the detection

node, the potential of this node changes in proportion to the amount of signal received. The change is sensed

by an MOS transistor and, after proper buffering, the signal is supplied to the output terminal of the image sensor.

The buffer amplifier converts charge into a video signal. Figure 8 shows the circuit diagram of the

charge-detection node and output amplifier. The detection nodes and amplifiers are placed a short distance

away from the edge of the storage area; therefore, each serial register contains four dummy elements that are

used to span the distance between the serial registers and the amplifiers.