Nexperia

74HC165; 74HCT165

8-bit parallel-in/serial out shift register

7. Functional description

Table 3. Function table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care; ↑ = LOW-to-HIGH clock transition.

Inputs

Qn registers

Outputs

Operating modes

PL

CE

CP

DS

D0 to D7 Q0

Q1 to Q6 Q7

Q7

L

X

X

X

L

L

L to L

L

H

parallel load

L

X

X

X

H

H

H to H

H

L

H

L

↑

l

X

L

q0 to q5

q6

q6

H

L

↑

h

X

H

q0 to q5

q6

q6

H

↑

L

l

X

L

q0 to q5

q6

q6

serial shift

H

↑

L

h

X

H

q0 to q5

q6

q6

H

H

X

X

X

q0

q1 to q6

q7

q7

hold "do nothing"

H

X

H

X

X

q0

q1 to q6

q7

q7

CE

CP

DS

PL

D0

D1

D2

D3

D4

D5

D6

D7

Q7

Q7

mna993

inhibit

serial shift

load

Fig. 6. Timing diagram

74HC_HCT165

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Product data sheet

Rev. 7 — 1 September 2021

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