Industry-Standard High-Speed CAN

Transceivers with ±80V Fault Protection

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11

(Figure 3). The transmitter becomes enabled upon

detecting a rising edge at TXD.

Receiver

The receiver reads differential inputs from the bus lines

(CANH, CANL) and transfers this data as a single-

ended output (RXD) to the CAN controller. It consists of

(CANH - CANL) with respect to an internal threshold of

0.7V), a logic-high is present.

The CANH and CANL common-mode range is greater

than ±12V. RXD is logic-high when CANH and CANL

are shorted or terminated and undriven.

+3.3V Logic Compatibility (MAX13054)

municate with +3.3V logic systems while operating from

a +5V supply. This provides a reduced input voltage

threshold to the TXD and STBY inputs, and provides a

logic-high output at RXD compatible with the microcon-

troller’s system voltage. The logic compatibility elimi-

nates longer propagation delay due to level shifting.

+5V logic systems.

Driver Output Protection

The current-limiting feature protects the transmitter out-

put stage against a short circuit to a positive and nega-

tive battery voltage. Although the power dissipation

increases during this fault condition, current-limit pro-

tection prevents destruction of the transmitter output

stage. Upon removal of a short, the CAN transceiver

resumes normal operation.

Thermal Shutdown

If the junction temperature exceeds +165°C, the driver

is switched off. The hysteresis is approximately 13°C,

TXD

RS

CANH

CANL

BUS STATE

RXD

Low

High

Low

Dominant

Low

High or Float

Recessive

High

Recessive

High

TXD

RS

CANH

CANL

BUS STATE

RXD

Low

High

Low

Dominant

Low

High or Float

Recessive

High

Recessive

High

Table 2. Transmitter and Receiver Truth Table (MAX13052)

TXD

STBY

CANH

CANL

BUS STATE

RXD

Low

≤ 0.8V

High

Low

Dominant

Low

High or Float

≤ 0.8V

Recessive

High

X

≥ 2V

Recessive

High

Table 3. Transmitter and Receiver Truth Table

(MAX13053)

(MAX13050/MAX13054)

TRANSMITTER

DISABLED

TRANSMITTER

ENABLED

TXD

Figure 3. Transmitter Dominant Timeout Timing Diagram

*For the MAX13054