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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9923ABBCZ датащи(PDF) 3 Page - Analog Devices |
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AD9923ABBCZ датащи(HTML) 3 Page - Analog Devices |
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3 / 88 page  AD9923A Rev. 0 | Page 3 of 88 SPECIFICATIONS Table 1. Parameter Conditions/Comments Min Typ Max Unit TEMPERATURE RANGE Operating −25 +85 °C Storage −65 +150 °C AFETG POWER SUPPLY VOLTAGES AVDD AFE analog supply 2.7 3.0 3.6 V TCVDD Timing Core Analog Supply 2.7 3.0 3.6 V RGVDD RG Driver 2.7 3.0 3.6 V HVDD HL, H1 to H4 Drivers 2.7 3.0 3.6 V DRVDD Data Output Drivers 2.7 3.0 3.6 V DVDD Digital 2.7 3.0 3.6 V V-DRIVER POWER SUPPLY VOLTAGES VDD1, VDD2 V-Driver Logic +2.7 +3.0 +3.6 V VH1, VH2 V-Driver High Supply +11.5 +15.0 +16.5 V VL1, VL2 V-Driver Low Supply −8.5 −7.5 −5.5 V VM1, VM2 V-Driver Mid Supply −1.5 0.0 +1.5 V VLL SUBCK Low Supply −8.5 −7.5 −5.5 V VMM SUBCK Mid Supply −4.0 0.0 +1.5 V AFETG POWER DISSIPATION Total 36 MHz, 3.0 V supply, 400 pF total H-load, 20 pF RG load 335 mW Standby 1 Mode 105 mW Standby 2 Mode 1 mW Standby 3 Mode 1 mW Power from HVDD Only1 130 mW Power from RGVDD Only 10 mW Power from AVDD Only 75 mW Power from TCVDD Only 40 mW Power from DVDD Only 75 mW Power from DRVDD Only 5 mW V-DRIVER POWER DISSIPATION2 VH1, VH2 = +15 V; VL1, VL2 = −7.5 V; VM1, VM2 = 0 V; VDD1, VDD2 = 3.3 V; all V-driver inputs tied low VH1, VH2 5 mW VL1, VL2 2.5 mW VM1, VM2 0 mW VDD1, VDD2 0.5 mW MAXIMUM CLOCK RATE (CLI) 36 MHz 1 The total power dissipated by the HVDD supply can be approximated using the equation Total HVDD Power = [CLOAD × HVDD × Pixel Frequency] × HVDD Reducing the H-load and/or using a lower HVDD supply reduces the power dissipation. CLOAD is the total capacitance seen by all H-outputs. 2 V-driver power dissipation depends on the frequency of operation and the load they are driving. All inputs to the V-driver were tied low for the measurements in Table 1. |
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