Preliminary Technical Data

AD9387NK

Rev. PrA | Page 5 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DVDD

D0

DE

HSYNC

VSYNC

CLK

S/PDIF

MCLK

SCLK

LRCLK

PVDD

PVDD

DVDD

D15

D16

D17

D18

D19

D20

D21

D22

D23

MCL

MDA

SDA

SCL

DDCSDA

DDCSCL

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AD9387NK

TOP VIEW

(Not to Scale)

NOTES

1. GND PADDLE ON BOTTOM OF PACKAGE.

+

Figure 2. 64-Lead LFCSP Pin Configuration (Top View)

A

B

C

D

E

F

G

J

H

K

10

8 7 6

3 2 1

95 4

BOTTOM VIEW

(Not to Scale)

Figure 3. 76-Ball BGA Configuration (Top View)

Table 3. Pin Function Descriptions

Pin No.

BGA

LFCSP

Mnemonic

Type1

Description

A1 to A10,

B1 to B10, C9,

C10, D9, D10

39 to 47,

50 to 63, 2

D[23:0]

I

Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels

from 1.8 V to 3.3 V.

D1

6

CLK

I

Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

C2

3

DE

I

Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.

C1

4

HSYNC

I

Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

D2

5

VSYNC

I

Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.

J3

18

EXT_SWG

I

Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this

pin and ground.

K3

20

HPD

I

Hot Plug Detect Signal. This indicates to the interface if the receiver is

connected. Supports CMOS logic levels from 1.8 V to 5.0 V.

E2

7

S/PDIF

I

S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a

Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.

E1

8

MCLK

I

V to 3.3 V.

F2, F1, G2, G1

9 to 12

I

H2

13

SCLK

I

H1

14

LRCLK

I

Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.

J7

26

PD/A0

I

polarity are set by the PD/A0 pin state when the supplies are applied to the

AD9387NK. Supports CMOS logic levels from 1.8 V to 3.3 V.

K1, K2

21, 22

TxC−/TxC+

O

Differential Clock Output. Differential clock output at pixel clock rate; TMDS

logic level.

K10, J10

30, 31

Tx2−/Tx2+

O

Differential Output Channel 2. Differential output of the red data at 10× the pixel

clock rate; TMDS logic level.