AD9237 datasheet(16/28 Pages) AD

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AD9237

Rev. 0 | Page 16 of 28

APPLYING THE AD9237

THEORY OF OPERATION

The AD9237 uses a calibrated, 11-stage pipeline architecture

with a patented input SHA implemented. Each stage of the

pipeline, excluding the last, consists of a low resolution flash

ADC connected to a switched capacitor digital-to-analog

converter (DAC) and an interstage residue amplifier (MDAC).

The MDAC magnifies the difference between the reconstructed

DAC output and the flash input for the next stage in the

pipeline. One bit of redundancy is used in each stage to facilitate

digital correction of flash errors. The last stage consists of a

flash ADC.

The pipelined architecture permits the first stage to operate on a

new input sample, while the remaining stages operate on preceding

samples. While the converter captures a new input sample every

clock cycle, it takes eight clock cycles for the conversion to be

fully processed and to appear at the output, as shown in Figure 2.

The input stage contains a differential SHA that can be ac- or

dc-coupled in differential or single-ended modes. The output-

staging block aligns the data, carries out the error correction,

and passes the data to the output buffers. The output buffers

are powered from a separate supply, allowing adjustment of

the output voltage swing. During power-down and stand-by

operation, the output buffers go into a high impedance state.

The ADC samples the analog input on the rising edge of

the clock. System disturbances just prior to, or immediately

following, the rising edge of the clock and/or excessive clock

jitter can cause the SHA to acquire the wrong input value and

should be minimized.

ANALOG INPUT AND REFERENCE OVERVIEW

The analog input to the AD9237 is a differential switched

capacitor SHA that has been designed for optimum

performance while processing a differential input signal.

The SHA input can support a wide common-mode range

and maintain excellent performance, as shown in Figure 34.

An input common-mode voltage of midsupply minimizes

signal-dependant errors and provides optimum performance.

Figure 35 shows the clock signal alternately switching the

SHA between sample mode and hold mode. When the SHA is

switched into sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current required from the output

stage of the driving source.

INPUT COMMON-MODE LEVEL (V)

3.0

2.5

2.0

1.5

1.0

0.5

2.5MHz SFDR

34.2MHz SFDR

2.5MHz SNR

34.2MHz SNR

Figure 34. AD9237-65 SNR/SFDR vs. Input Common-Mode Level

In addition, a small shunt capacitor placed across the inputs

provides dynamic charging currents. This passive network

creates a low-pass filter at the ADC’s input; therefore, the

precise values are dependant on the application. In IF under-

sampling applications, the shunt capacitor(s) should be reduced

or removed depending on the input frequency. In combination

with the driving source impedance, the capacitors limit the

input bandwidth.

VIN+

VIN–

CPAR

5pF

Figure 35. Switched-Capacitor SHA Input

For best dynamic performance, the source impedances driving

VIN+ and VIN– should be matched so that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC.

An internal differential reference buffer creates positive and

negative reference voltages, REFT and REFB, that define the

span of the ADC core.

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