AD9211 datasheet(17/21 Pages) AD

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Preliminary Technical Data

AD9211

Rev. PrA | Page 17 of 21

Figure 14. AD9211-250, Supply Current vs. fSAMPLE for fIN = 10.3 MHz

By asserting the PDWN pin high, the AD9211 is placed in

standby mode. In this state, the ADC typically dissipates

1 mW even if the CLK and analog inputs are static. During

standby, the output drivers are placed in a high impedance state.

Reasserting the PDWN pin low returns the AD9211 into its

normal operational mode.

An additional stand by mode is supported by means of varying

the clock input. When the clock rate falls below 20MHz, the

AD9211 will assume a standby state. In this case, the biasing

network and internal reference remain on but digital circuitry is

powered down. Upon reactivating the clock, the AD9211 will

resume normal operation after allowing for the pipeline latency.

DIGITAL OUTPUTS

The AD9228’s differential outputs conform to the ANSI-644

LVDS standard on default power up. The LVDS driver current

is derived on-chip and sets the output current at each output

equal to a nominal 3.5 mA. A 100 Ω differential termination

resistor placed at the LVDS receiver inputs results in a nominal

350 mV swing at the receiver.

The AD9211’s LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capa-

bility for superior switching performance in noisy environ-

ments. Single point-to-point net topologies are recommended

with a 100 Ω termination resistor placed as close to the receiver

as possible. It is recommended to keep the trace length no

longer than 12 inches and to keep differential output traces

close together and at equal lengths.

The format of the output data is offset binary. An example of

the output coding format can be found in Table 7.

Table 7. Digital Output Coding

Code

(VIN+) − (VIN−),

Input Span =

1.252 V p-p (V)

Digital Output

Offset Binary

(D9 ... D0)

1024

1.000

11 1111 1111

512

10 0000 0000

511

−0.000488

01 1111 1111

−1.00

00 0000 0000

As detailed in Interfacing to ADC SPI, the data format can be

selected for either offset binary or twos complement, or Gray

code (SPI access only).

Out-of-Range (OTR)

An out-of-range condition exists when the analog input voltage

is beyond the input range of the ADC. OTR is a digital output

that is updated along with the data output corresponding to the

particular sampled input voltage. Thus, OTR has the same

pipeline latency as the digital data. OTR is low when the analog

input voltage is within the analog input range and high when

the analog input voltage exceeds the input range as shown in

Figure 15. OTR will remain high until the analog input returns

to within the input range and another conversion is completed.

By logically AND-ing OTR with the MSB and its complement,

over-range high or under-range low conditions can be detected.

Figure 15. OTR Relation to Input Voltage and Output Data for

AD9230/AD9211

TIMING

The AD9211 provides latched data outputs with a pipeline delay

of five clock cycles. Data outputs are available one propagation

delay (tPD) after the rising edge of the clock signal.

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