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BSP92 датащи(PDF) 3 Page - NXP Semiconductors

номер детали BSP92
подробное описание детали  P-channel enhancement mode vertical D-MOS transistor
PDF  8 Pages
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производитель  PHILIPS [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

BSP92 датащи(HTML) 3 Page - NXP Semiconductors

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April 1995
3
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BSP92
CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
−V(BR)DSS
drain-source breakdown voltage
−ID = 10 µA; VGS = 0
240
−−
V
−I
DSS
drain-source leakage current
−VDS = 200 V; VGS = 0
−−
1
µA
±I
GSS
gate-source leakage current
±VGS = 20 V; VDS = 0
−−
100
nA
−VGS(th)
gate-source threshold voltage
−ID = 1 mA; VGS = VDS
0.8
2V
−V
GS
gate-source voltage
−ID = 50 mA; −VDS = 5 V
0.8
2.8
V
RDS(on)
drain-source on-resistance
−ID = 180 mA; −VGS = 10 V
10
20
−ID = 100 mA; −VGS = 5 V
−−
18
−I
D = 25 mA; −VGS = 2.8 V
−−
20
 Y
fs
transfer admittance
−ID = 180 mA; −VDS = 25 V
100
200
mS
Ciss
input capacitance
−VDS = 25 V; VGS = 0; f = 1 MHz
65
90
pF
Coss
output capacitance
−VDS = 25 V; VGS = 0; f = 1 MHz
20
30
pF
Crss
feedback capacitance
−VDS = 25 V; VGS = 0; f = 1 MHz
615
pF
Switching times (see Figs 3 and 4)
ton
turn-on time
−ID = 250 mA; −VDD = 50 V;
−VGS = 0 to 10 V
510
ns
toff
turn-off time
−ID = 250 mA; −VDD = 50 V;
−VGS = 0 to 10 V
20
30
ns
Fig.2 Power derating curve.
handbook,
0
50
100
200
2
0
1.6
150
1.2
0.8
0.4
MBB693
Ptot
(W)
Tamb (°C)
Fig.3 Switching times test circuit.
handbook, halfpage
MBB689
50
VDD = −50 V
ID
0 V
−10 V



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