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PCK9448 датащи(PDF) 3 Page - NXP Semiconductors |
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PCK9448 датащи(HTML) 3 Page - NXP Semiconductors |
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3 / 20 page ![]() 9397 750 12534 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 29 November 2005 3 of 20 Philips Semiconductors PCK9448 3.3 V/2.5 V LVCMOS 1 : 12 clock fan-out buffer 5. Pinning information 5.1 Pinning 5.2 Pin description Fig 2. Pin configuration for LQFP32 PCK9448BD CLK_SEL GND CCLK Q4 PCLK VCC PCLK Q5 CLK_STOP GND OE Q6 VCC VCC GND Q7 002aaa721 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 Table 2: Pin description Symbol Pin Type Description CLK_SEL 1 I clock input select CCLK 2 I alternative clock signal input PCLK 3 I clock signal input PCLK 4 I clock signal input, active LOW CLK_STOP 5 I clock output enable/disable, active LOW OE 6 I output enable/disable (high-impedance, 3-state) Q0 to Q11 31, 29, 27, 25, 23, 21, 19, 17, 15, 13, 11, 9 O clock outputs GND 8, 12, 16, 20, 24, 28, 32 ground negative power supply (GND) VCC 7, 10, 14, 18, 22, 26, 30 power Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation. |
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