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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PCA9671D датащи(PDF) 21 Page - NXP Semiconductors |
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PCA9671D датащи(HTML) 21 Page - NXP Semiconductors |
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21 / 34 page  PCA9671_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 20 December 2006 21 of 34 NXP Semiconductors PCA9671 Remote 16-bit I/O expander for Fm+ I2C-bus with reset 13. Dynamic characteristics [1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [3] Cb = total capacitance of one bus line in pF. [4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region SCL’s falling edge. Table 6. Dynamic characteristics VDD = 2.3 V to 5.5 V; VSS =0V; Tamb = −40 °Cto+85 °C; unless otherwise specified. Symbol Parameter Conditions Standard-mode I2C-bus Fast-mode I2C-bus Fast-mode Plus I2C-bus Unit Min Max Min Max Min Max fSCL SCL clock frequency 0 100 0 400 0 1000 kHz tBUF bus free time between a STOP and START condition 4.7 - 1.3 - 0.5 - µs tHD;STA hold time (repeated) START condition 4.0 - 0.6 - 0.26 - µs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - 0.26 - µs tSU;STO set-up time for STOP condition 4.0 - 0.6 - 0.26 - µs tHD;DAT data hold time 0 - 0 - 0 - ns tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 0.05 0.45 µs tVD;DAT data valid time [2] 300 - 50 - 50 450 ns tSU;DAT data set-up time 250 - 100 - 50 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - 0.5 - µs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - 0.26 - µs tf fall time of both SDA and SCL signals [4][5] - 300 20 + 0.1Cb [3] 300 - 120 ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 - 120 ns tSP pulse width of spikes that must be suppressed by the input filter [6] - 50 - 50 - 50 ns Port timing; CL ≤ 100 pF (see Figure 17 and Figure 16) tv(Q) data output valid time - 4 - 4 - 4 µs tsu(D) data input set-up time 0 - 0 - 0 - µs th(D) data input hold time 4 - 4 - 4 - µs Reset timing (see Figure 26) tw(rst) reset pulse width 4 - 4 - 4 - ns trec(rst) reset recovery time 0 - 0 - 0 - ns trst reset time 100 - 100 - 100 - ns |
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