Philips Semiconductors

Product data sheet

PCA9516A

2004 Sep 29

5

FUNCTIONAL DESCRIPTION

similar bus systems to be expanded with only one repeater delay

and no functional degradation of system performance.

The PCA9516A contains five bi-directional, open drain buffers

specifically designed to support the standard low-level-contention

stretching, the PCA9516A acts like five pairs of non-inverting, open

drain buffers, one for SDA and one for SCL.

Enable

The enable pins EN1 through EN4 are active HIGH and have

internal pull-up resistors. Each enable pin ENn controls its

associated SDAn and SCLn ports. When LOW, the ENn pin blocks

the inputs from SDAn and SCLn as well as disabling the output

drivers on the SDAn and SCLn pins. The enable pins should only

change state when both the global bus and the local port are in an

idle state to prevent system failures.

The active HIGH enable pins allow the use of open drain drivers

which can be wire-ORed to create a distributed enable where either

centralized control signal (master) or spoke signal (submaster) can

enable the channel when it is idle.

provide the logic HIGH levels on the Buffered bus. (Standard

pull-up resistors depends on the system, but each side of the

repeater must have a pull-up resistor. This part is designed to work

where standard mode devices and multiple masters are possible.

Please see Application Note AN255

and Expanders” for additional information on sizing resistors and

precautions when using more than one PCA9515A/PCA9516A in a

system or using the PCA9515A/16A in conjunction with the P82B96.

APPLICATION INFORMATION

A typical application is shown in Figure 4. In this example, the

connected to a 5 V bus. All buses run at 100 kHz unless slave 3 is

isolated and then the master bus and slave 1 and 2 can run at

400 kHz.

Any segment of the hub can talk to any other segment of the hub.

Bus masters and slaves can be located on all five segments with

400 pF load allowed on each segment.

Unused ports should be isolated by holding the enable pin to GND

resistors. The primary bus master is normally connected to

SDA0/SCL0. If the SDA0/SCL0 port is not used, the pins need to be

The PCA9516A is 5.5 V tolerant so it does not require any additional

circuitry to translate between the different bus voltages.

When one side of the PCA9516A is pulled LOW by a device on the

causes an internal driver on the other side to turn on, thus causing

the other side to also go LOW. The side driven LOW by the

SW02249

BUS

MASTER

SLAVE 1

PCA9516A

SDA

SDA0

SDA

SCL

SCL0

SCL

EN1

3.3 V

5 V

SDA1

SCL1

EN2

EN3

EN4

SLAVE 2

SDA

SCL

3.3 V

SDA2

SCL2

SLAVE 3

SDA

SCL

5 V

SDA3

SCL3

3.3 V or 5 V

SDA4

SCL4

400 kHz

400 kHz

400 kHz

100 kHz

Figure 4. Typical application