P89LPC9408 datasheet(21/69 Pages) PHILIPS

21 / 69 page

P89LPC9408_1

Product data sheet

Rev. 01 — 16 December 2005

21 of 69

Philips Semiconductors

P89LPC9408

8-bit two-clock 80C51 core with 32 segment

× 4 LCD driver, 10-bit ADC

7.7 CPU Clock (CCLK) wake-up delay

The P89LPC9408 has an internal wake-up timer that delays the clock until it stabilizes

depending on the clock source used. If the clock source is any of the three crystal

selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus

µsto100 µs. If the clock source is either the internal RC oscillator, watchdog oscillator,

or external clock, the delay is 224 OSCCLK cycles plus 60

µsto100 µs.

7.8 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

7.9 Low power select

The P89LPC9408 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is

8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power

consumption further. On any reset, CLKLP is logic 0 allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

Fig 6.

Block diagram of oscillator control

÷2

002aab102

RTC

ADC0

CPU

WDT

DIVM

CCLK

UART

OSCCLK

I2C-BUS

PCLK

TIMER 0 AND

TIMER 1

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

XTAL1

XTAL2

OSCILLATOR

WATCHDOG

OSCILLATOR

(7.3728 MHz

± 1 %)

PCLK

RCCLK

SPI

CCU

× PLL

(400 kHz

+30 % −20 %)

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