P89LPC9401 datasheet(9/59 Pages) PHILIPS

9 / 59 page

P89LPC9401_1

Preliminary data sheet

Rev. 01 — 5 September 2005

9 of 59

Philips Semiconductors

P89LPC9401

8-bit two-clock 80C51 microcontroller with 32 segment

× 4 LCD driver

P1.5/RST

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during power-on or if selected via UCFG1. When

functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O

ports and peripherals to take on their default states, and the processor begins

execution at address 0. Also used during a power-on sequence to force ISP mode.

When using an oscillator frequency above 12 MHz, the reset input function of

P1.5 must be enabled. An external circuit is required to hold the device in reset at

power-up until VDD has reached its speciﬁed level. When system power is

removed VDD will fall below the minimum speciﬁed operating voltage. When

using an oscillator frequency above 12 MHz, in some applications, an external

brownout detect circuit may be required to hold the device in reset when VDD falls

below the minimum speciﬁed operating range.

P1.6

I/O

P1.6 — Port 1 bit 6.

P1.7

I/O

P1.7 — Port 1 bit 7.

P2.0 to P2.3,

P2.5

I/O

Port 2: Port 2 is an 5-bit I/O port with a user-conﬁgurable output type. During reset

Port 2 latches are conﬁgured in the input only mode with the internal pull-up disabled.

The operation of Port 2 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 7.13.1 “Port

conﬁgurations” and Table 11 “Static electrical characteristics” for details.

All pins have Schmitt trigger inputs.

Port 2 also provides various special functions as described below:

P2.0

I/O

P2.0 — Port 2 bit 0.

P2.1

I/O

P2.1 — Port 2 bit 1.

P2.2/MOSI

I/O

P2.2 — Port 2 bit 2.

I/O

MOSI — SPI master out slave in. When conﬁgured as master, this pin is output; when

conﬁgured as slave, this pin is input.

P2.3/MISO

I/O

P2.3 — Port 2 bit 3.

I/O

MISO — When conﬁgured as master, this pin is input, when conﬁgured as slave, this

pin is output.

P2.5/SPICLK

I/O

P2.5 — Port 2 bit 5.

I/O

SPICLK — SPI clock. When conﬁgured as master, this pin is output; when conﬁgured

as slave, this pin is input.

P3.0 to P3.1

I/O

Port 3: Port 3 is a 2-bit I/O port with a user-conﬁgurable output type. During reset

Port 3 latches are conﬁgured in the input only mode with the internal pull-up disabled.

The operation of Port 3 pins as inputs and outputs depends upon the port conﬁguration

selected. Each port pin is conﬁgured independently. Refer to Section 7.13.1 “Port

conﬁgurations” and Table 11 “Static electrical characteristics” for details.

All pins have Schmitt triggered inputs.

Port 3 also provides various special functions as described below:

P3.0/XTAL2/

CLKOUT

I/O

P3.0 — Port 3 bit 0.

XTAL2 — Output from the oscillator ampliﬁer (when a crystal oscillator option is

selected via the ﬂash conﬁguration.

CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It

can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or

external clock input, except when XTAL1/XTAL2 are used to generate clock source for

the RTC/system timer.

Table 3:

Pin description …continued

Symbol

Type Description

P89LPC9401 датащи(PDF) 9 Page - NXP Semiconductors

P89LPC9401 датащи(HTML) 9 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

датащи скачать

ссылки URL