AD7366

Preliminary Technical Data

Rev. PrG | Page 16 of 17

SERIAL INTERFACE

Figure 9 shows the detailed timing diagram for serial inter-

facing to the AD7366. On the falling edge of CONVST the

AD7366 will simultaneously convert the selected channels.

These conversions are performed using the on-chip oscillator.

After the falling edge of CONVST the BUSY signal goes high,

indicating the conversion has started. It returns low once the

conversion has been completed. The data can now be read from

the

CS and SCLK signals are required to transfer data from the

AD7366. The AD7366 has two output pins corresponding to

each ADC. Data can be read from the AD7366 using both

choice can be used. The SCLK input signal provides the

clock source for the serial interface. The CS goes low to

access data from the AD7366. The falling edge of CS takes

the bus out of three-state and clocks out the MSB of the

conversion result. The data stream consists of 12 bits of data

MSB first. The first bit of the conversion result is valid on the

first SCLK falling edge after the CS falling edge. The

subsequent 11 bits of data are clocked out on the falling edge

of the SCLK signal. A minimum of 12 Clock pulses must be

9

shows how a 12 SCLK read is used to access the conversion

results.

On the rising edge of CS, the conversion will be terminated

brought high, but is instead held low for a further 12 SCLK

line in use goes back into three-state on the rising edge of CS

If the falling edge of SCLK coincides with the falling edge of

CS, then the falling edge of SCLK is not acknowledged by

the AD7366, and the next falling edge of the SCLK will be

the first registered after the falling edges of the CS.

The CS pin can be brought low before the BUSY signal goes

low to indicate the end of a conversion. The data bus is bought

out of three-state by taking the CS pin low. This feature can be

utilized to ensure that the MSB is valid on the falling edge of

this.

CS

SCLK

1

5

12

DOUTA

DOUTB

3-STATE

2

34

3-STATE

DB11

DB10

DB2

DB0

DB1

DB9

DB8

Figure 9. Serial Interface Timing diagram

CS

SCLK

1

5

11

THREE-

STATE

2

34

12

THREE-

STATE

10

13

24