Nexperia

74LVC02A

Quad 2-input NOR gate

12. Abbreviations

Table 9. Abbreviations

Acronym

Description

CDM

Charged Device Model

CMOS

Complementary Metal Oxide Semiconductor

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 10. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

74LVC02A v.10

20210917

Product data sheet

-

74LVC02A v.9

Modifications:

• Type number 74LVC02ADB (SOT337-1/SSOP14) removed.

• Section 1 updated.

74LVC02A v.9

20200824

Product data sheet

-

74LVC02A v.8

Modifications:

• The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

• Table 4: Derating values for Ptot total power dissipation have been updated.

• Package outline drawing of SOT762-1 (Fig. 10) updated.

74LVC02A v.8

20111116

Product data sheet

-

74LVC02A v.7

Modifications:

• Legal pages updated.

• Table 6, bodyrow ΔICC: condition VCC changed.

74LVC02A v.7

20111019

Product data sheet

-

74LVC02A v.6

74LVC02A v.6

20110809

Product data sheet

-

74LVC02A v.5

74LVC02A v.5

20040312

Product specification

-

74LVC02A v.4

74LVC02A v.4

20030501

Product specification

-

74LVC02A v.3

74LVC02A v.3

20020305

Product specification

-

74LVC02A v.2

74LVC02A v.2

19980428

Product specification

-

74LVC02A v.1

74LVC02A v.1

19970811

Product specification

-

-

74LVC02A

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 10 — 17 September 2021

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