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74LVC02A датащи(PDF) 5 Page - Nexperia B.V. All rights reserved |
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74LVC02A датащи(HTML) 5 Page - Nexperia B.V. All rights reserved |
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5 / 12 page ![]() Nexperia 74LVC02A Quad 2-input NOR gate 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 7. -40 °C to +85 °C -40 °C to +125 °C Symbol Parameter Conditions Min Typ[1] Max Min Max Unit nA, nB to nY; see Fig. 6 [2] VCC = 1.2 V - 14 - - - ns VCC = 1.65 V to 1.95 V 0.5 4.0 8.6 0.5 10.1 ns VCC = 2.3 V to 2.7 V 1.0 2.4 4.9 1.0 5.7 ns VCC = 2.7 V 1.0 2.5 5.1 1.0 6.5 ns tpd propagation delay VCC = 3.0 V to 3.6 V 1.0 2.2 4.4 1.0 5.5 ns tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns per gate; VI = GND to VCC [4] VCC = 1.65 V to 1.95 V - 2.5 - - - pF VCC = 2.3 V to 2.7 V - 5.7 - - - pF CPD power dissipation capacitance VCC = 3.0 V to 3.6 V - 8.5 - - - pF [1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL x VCC 2 x fo) = sum of the outputs 74LVC02A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 — 17 September 2021 5 / 12 |
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