ADV7344 datasheet(45/88 Pages) AD

45 / 88 page

ADV7344

Rev. 0 | Page 45 of 88

ENHANCED DEFINITION/HIGH DEFINITION ONLY

Subaddress 0x01, Bits[6:4] = 001 or 010

Enhanced definition (ED) or high definition (HD) YCrCb data

can be input in either 4:2:2 or 4:4:4 formats. If desired, dual data

rate (DDR) pixel data inputs can be employed (4:2:2 format only).

Enhanced definition (ED) or high definition (HD) RGB data

can be input in 4:4:4 format (single data rate only).

The clock signal must be provided on the CLKIN_A pin. Input

synchronization signals are provided on the P_HSYNC,

P_VSYNC and P_BLANK pins.

16-/20-Bit 4:2:2 YCrCb Mode (SDR)

Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1

In 16-/20-bit 4:2:2 YCrCb input mode, the Y pixel data is input on

Pin Y9 to Pin Y2/Y0, with Y0 being the LSB in 20-bit input mode.

The CrCb pixel data is input on Pin C9 to Pin C2/C0, with C0

being the LSB in 20-bit input mode.

8-/10-Bit 4:2:2 YCrCb Mode (DDR)

Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 1

In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is

input on Pin Y9 to Pin Y2/Y0 upon either the rising or falling

edge of CLKIN_A. Y0 is the LSB in 10-bit input mode.

The CrCb pixel data is also input on Pin Y9 to Pin Y2/Y0 upon the

opposite edge of CLKIN_A. Y0 is the LSB in 10-bit input mode.

Whether the Y data is clocked in upon the rising or falling edge

of CLKIN_A is determined by Subaddress 0x01, Bits[2:1] (see

Figure 52 and Figure 53).

3FF

Cr0

CLKIN_A

NOTES

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.

Y[9:0]

Cb0

Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A

3FF

Cb0

Cr0

CLKIN_A

Y[9:0]

NOTES

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.

Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B

24-/30-Bit 4:4:4 YCrCb Mode

Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 0

In 24-/30-bit 4:4:4 YCrCb input mode, the Y pixel data is input on

Pin Y9 to Pin Y2/Y0, with Y0 being the LSB in 30-bit input mode.

The Cr pixel data is input on Pin S9 to Pin S2/S0, with S0 being

the LSB in 30-bit input mode.

The Cb pixel data is input on Pin C9 to Pin C2/C0, with C0

being the LSB in 30-bit input mode.

24-/30-Bit 4:4:4 RGB Mode

Subaddress 0x35, Bit 1 = 1

In 24-/30-bit 4:4:4 RGB input mode, the red pixel data is input

on Pin S9 to Pin S2/S0, the green pixel data is input on Pin Y9 to

Pin Y2/Y0, and the blue pixel data is input on Pin C9 to Pin C2/C0.

S0, Y0, and C0 are the respective bus LSBs in 30-bit input mode.

MPEG2

DECODER

CLKIN_A

C[9:0]

S[9:0]

Y[9:0]

INTERLACED TO

PROGRESSIVE

YCrCb

ADV7344

P_VSYNC,

P_HSYNC,

P_BLANK

Figure 54. ED/HD Only Example Application

SIMULTANEOUS STANDARD DEFINITION AND

ENHANCED DEFINITION/HIGH DEFINITION

Subaddress 0x01, Bits[6:4] = 011 or 100

The ADV7344 is able to simultaneously process SD 4:2:2 YCrCb

data and ED/HD 4:2:2 YCrCb data. The 27 MHz SD clock

signal must be provided on the CLKIN_A pin. The ED/HD

clock signal must be provided on the CLKIN_B pin. SD input

synchronization signals are provided on the S_HSYNC and

S_VSYNC pins. ED/HD input synchronization signals are

provided on the P_HSYNC, P_VSYNC and P_BLANK pins.

SD 8-/10-Bit 4:2:2 YCrCb and ED/HD-SDR 16-/20-Bit

4:2:2 YCrCb

The SD 8-/10-bit 4:2:2 YCrCb pixel data is input on Pin S9 to

Pin S2/S0, with S0 being the LSB in 10-bit input mode.

The ED/HD 16-/20-bit 4:2:2 Y pixel data is input on Pin Y9 to

Pin Y2/Y0, with Y0 being the LSB in 20-bit input mode.

The ED/HD 16-/20-bit 4:2:2 CrCb pixel data is input on Pin C9

to Pin C2/C0, with C0 being the LSB in 20-bit input mode.

SD 8-/10-Bit 4:2:2 YCrCb and ED/HD-DDR 8-/10-Bit

4:2:2 YCrCb

The SD 8-/10-bit 4:2:2 YCrCb pixel data is input on Pin S9 to

Pin S2/S0, with S0 being the LSB in 10-bit input mode.

The ED/HD-DDR 8-/10-bit 4:2:2 Y pixel data is input on Pin Y9

to Pin Y2/Y0 upon the rising or falling edge of CLKIN_B. Y0 is

the LSB in 10-bit input mode.

The ED/HD-DDR 8-/10-bit 4:2:2 CrCb pixel data is also input

on Pin Y9 to Pin Y2/Y0 upon the opposite edge of CLKIN_B.

Y0 is the LSB in 10-bit input mode.

Whether the ED/HD Y data is clocked in upon the rising or

falling edge of CLKIN_B is determined by Subaddress 0x01,

Bits[2:1] (See the input sequence shown in Figure 52 and

Figure 53).

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