ADV7342 datasheet(51/88 Pages) AD

51 / 88 page

ADV7342/ADV7343

Rev. 0 | Page 51 of 88

Programming the FSC

The subcarrier frequency register value is divided into four FSC

registers as shown in the previous example. The four subcarrier

frequency registers must be updated sequentially, starting with

Subcarrier Frequency Register 0 and ending with Subcarrier

Frequency Register 3. The subcarrier frequency updates only

after the last subcarrier frequency register byte has been

received by the ADV7342/ADV7343.

Typical FSC Values

Table 38 outlines the values that should be written to the

subcarrier frequency registers for NTSC and PAL B/D/G/H/I.

Table 38. Typical FSC Values

Subaddress

Description

NTSC

PAL B/D/G/H/I

0x8C

FSC0

0x1F

0xCB

0x8D

FSC1

0x7C

0x8A

0x8E

FSC2

0xF0

0x09

0x8F

FSC3

0x21

0x2A

SD NONINTERLACED MODE

Subaddress 0x88, Bit 1

The ADV7342/ADV7343 support a SD noninterlaced mode.

Using this mode, progressive inputs at twice the frame rate of

NTSC and PAL (240p/59.94 Hz and 288p/50 Hz, respectively)

can be input into the ADV7342/ADV7343. The SD noninterlaced

mode can be enabled using Subaddress 0x88, Bit 1.

A 27 MHz clock signal must be provided on the CLKIN_A pin.

Embedded EAV/SAV timing codes or external horizontal and

vertical synchronization signals provided on the S_HSYNC and

S_VSYNC pins can be used to synchronize the input pixel data.

All input configurations, output configurations and features

available in NTSC and PAL modes are available in SD non-

interlaced mode.

For 240p/59.94 Hz input, the ADV7342/ADV7343 should be

configured for NTSC operation and Subaddress 0x88, Bit 1

should be set to 1.

For 288p/50 Hz input, the ADV7342/ADV7343 should be

configured for PAL operation and Subaddress 0x88, Bit 1

should be set to 1.

SD SQUARE PIXEL MODE

Subaddress 0x82, Bit 4

The ADV7342/ADV7343 can be used to operate in square pixel

mode (Subaddress 0x82, Bit 4). For NTSC operation, an input

clock of 24.5454 MHz is required. Alternatively, for PAL

operation, an input clock of 29.5 MHz is required.

The internal timing logic adjusts accordingly for square pixel

mode operation. In square pixel mode, the timing diagrams

shown in Figure 63 and Figure 64 apply.

Y F

Y C

EAV CODE

SAV CODE

ANCILLARY DATA

(HANC)

4 CLOCK

272 CLOCK

1280 CLOCK

4 CLOCK

344 CLOCK

1536 CLOCK

END OF ACTIVE

VIDEO LINE

START OF ACTIVE

VIDEO LINE

ANALOG

VIDEO

INPUT PIXELS

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

Figure 63. Square Pixel Mode EAV/SAV Embedded Timing

FIELD

PIXEL

DATA

PAL = 308 CLOCK CYCLES

NTSC = 236 CLOCK CYCLES

HSYNC

Figure 64. Square Pixel Mode Active Pixel Timing

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