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AD5644R датащи(PDF) 7 Page - Analog Devices

номер детали AD5644R
подробное описание детали  Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference
PDF  28 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD5644R датащи(HTML) 7 Page - Analog Devices

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TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.1
Table 5.
Limit at TMIN, TMAX
Parameter
VDD = 2.7 V to 5.5 V
Unit
Conditions/Comments
t12
20
ns min
SCLK cycle time
t2
9
ns min
SCLK high time
t3
9
ns min
SCLK low time
t4
13
ns min
SYNC to SCLK falling edge setup time
t5
5
ns min
Data setup time
t6
5
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
15
ns min
Minimum SYNC high time
t9
13
ns min
SYNC rising edge to SCLK fall ignore
t10
0
ns min
SCLK falling edge to SYNC fall ignore
1 Guaranteed by design and characterization, not production tested.
2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.
TIMING DIAGRAM
DB0
DB23
t10
SCLK
SYNC
DIN
t1
t9
t7
t2
t3
t6
t5
t4
t8
Figure 2. Serial Write Operation



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