Preliminary Technical Data

AD5522

Rev. PrL | Page 37 of 45

READBACK OF ALARM STATUS REGISTER

The Alarm Status register is a READ only register that gives information on temperature, clamp and guard alarm events. In the event the

Guard and Clamp alarm functions are not used, (the alarm function may be switched off in the System Control Register). In this case, the

Temperature alarm status is also available in the contents of any of the four PMU readback registers.

Table 26. Alarm Status Readback Register

Bit

Bit name

Description

23 (MSB)

MODE1

1

22

MODE0

1

ALARM STATUS READBACK REGISTER SPECIFIC BITS

21

LTMPALM

20

TMPALM

TMPALM corresponds to the open drain TMPALM output pin which flags the user of a temperature event

exceeding the default or user programmed level. The temperature alarm is a per device alarm, and latched

(LTMPALM) and unlatched (TMPALM) bits tell a temperature event occurred and if the alarm still exists (if

the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user

must write to the CLEAR bit in the PMU register.

19

LG0

18

G0

17

LG1

16

G1

15

LG2

14

G2

13

LG3

12

G3

LGx is the per channel latched Guard Alarm bit and Gx is an unlatched alarm bit. These bits give

information on which channel flagged an alarm on the open drain alarm CGALM pin and if the alarm

condition still exists.

11

LC0

10

C0

9

LC1

8

C1

7

LC2

6

C2

5

LC3

4

C3

LCx is a per channel latched Clamp alarm bit and Cx is the unlatched alarm bit. These bits give

information on which channel flagged an alarm on the open drain alarm CGALM pin and if the alarm

condition still exists.

3 to 0 (LSB)

Unused Readback bits

Will be loaded with zeros.

READBACK OF DAC REGISTER

The DAC readback function is a 24 bit word, mode, address and DAC data bits.

Table 27. DAC Register Readback

Bit

Bit name

Description

23 (MSB)

MODE1

0

22

MODE0

0

DAC READBACK REGISTER SPECIFIC BITS

21 to 16

A5, A4, A3, A2, A1

Address Bits indicating the DAC register that is read.

15 to 0 (LSB)

D15 to D0

Contents of the addressed DAC register (x1, m or c).