AD5362BSTZ datasheet(16/25 Pages) AD

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AD5362/AD5363

Preliminary Technical Data

Rev. P

rF | Page 16 of 25

DAC outputs will remain at SIGGND until the X, M or C

registers are updated and LDAC is taken low.

CLEAR FUNCTION

CLR is an active low input which should be high for normal

operation. The CLR pin has in internal 500kΩ pull-down

resistor. When CLR is low, the input to each of the DAC output

buffer stages, VOUT0 to VOUT7, is switched to the externally

set potential on the relevant SIGGND pin. While CLR is low, all

LDAC pulses are ignored. When CLR is taken high again, the

DAC outputs remain cleared until LDAC is taken low. The

contents of input registers and DAC registers 0 to 7 are not

affected by taking CLR low. To prevent glitches appearing on

the outputs CLR should be brought low whenever the output

span is adjusted by writing to the offset DAC.

BUSY AND LDAC FUNCTIONS

The value of an X2 (A or B) register is calculated each time the

user writes new data to the corresponding X1, C, or M registers.

During the calculation of X2, the BUSY output goes low. While

BUSY is low, the user can new data to the X1, M, or C registers,

provided the first stage of the calculation is complete (see the

The BUSY pin is bidirectional and has a 50 kΩ internal pullup

resistor. Where multiple AD5362 or AD5363 devices may be

used in one system the BUSY pins can be tied together. This is

useful where it is required that no DAC in any device is updated

until all other DACs are ready. When each device has finished

updating the X2 (A or B) registers it will release the BUSY pin.

If another device hasn’t finished updating its X2 registers it will

hold BUSY low, thus delaying the effect of LDAC going low.

The DAC outputs are updated by taking the LDAC input low. If

LDAC goes low while BUSY is active, the LDAC event is stored

and the DAC outputs update immediately after BUSY goes

high. A user can also hold the LDAC input permanently low. In

this case, the DAC outputs update immediately after BUSY

goes high. BUSY also goes low, for approximately 500ns,

whenever the A/B Select Registers are written to.

As described later, the AD5362/AD5363 has flexible addressing

that allows writing of data to a single channel, all channels in a

group, or all channels in the device. This means that several

is only one multiplier shared between 8 channels, this task must

be done sequentially, so the length of the BUSY pulse will vary

according to the number of channels being updated.

Table 7. BUSY Pulse Widths

Action

BUSY Pulse Width

(µs max)

Loading X1A, X1B, C, or M to 1 channel

1.25

Loading X1A, X1B, C, or M to 2 channels

1.75

Loading X1A, X1B, C, or M to 8 channels

4.75

BUSY Pulse Width = ((Number of Channels +1) × 500ns) +250ns

The AD5362/AD5363 contains an extra feature whereby a DAC

written to since the last time LDAC was brought low. Normally,

when LDAC is brought low, the DAC registers are filled with

the contents of the X2A or X2B registers, depending on the

setting of the A/B Select Registers. However the

AD5362/AD5363 updates the DAC register only if the X2 data

has changed, thereby removing unnecessary digital crosstalk.

BIN/2S COMP PIN

The BIN/2SCOMP pin determines if the input data is

interpreted as offset binary or 2’s complement. If this pin is low,

then the data is binary. If it is 1, the data is interpreted as 2’s

complement. This affects only the X, C, and Offset DAC

registers. The M register data and all control and command

data is interpreted as straight binary.

TEMPERATURE SENSOR

The on-chip temperature sensor provides a voltage output at

the TEMP_OUT pin that is linearly proportional to the

Centigrade temperature scale. The typical accuracy of the

temperature sensor is ±1°C at +25°C and ±5°C over the −40°C

to +85°C range. Its nominal output voltage is 1.5V at +25°C,

varying at 5 mV/°C, giving a typical output range of 1.175V to

1.9 V over the full temperature range. Its low output

impedance, low self heating, and linear output simplify

interfacing to temperature control circuitry and A/D

converters.

MONITOR FUNCTION

The AD5362/AD5363 contains a channel monitor function that

consists of an analog multiplexer addressed via the serial

interface, allowing any channel output to be routed to this pin

for monitoring using an external ADC. In addition, two

monitor inputs, MON_IN0 and MON_IN1 are provided,

which can also be routed to MON_OUT. The monitor function

is controlled by the Monitor Register, which allows the monitor

output to be enabled or disabled, and selection of a DAC

channel or one of the monitor pins. When disabled, the

monitor output is high impedance, so several monitor outputs

may be connected in parallel and only one enabled at a time.

Table 8 shows the control register settings relevant to the

monitor function.

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