Preliminary Technical Data

AD5370

Rev. P

rF | Page 19 of 24

REGISTER UPDATE RATES

As mentioned previously the value of the X2 (A or B) register is

calculated each time the user writes new data to the

corresponding X1, C or M registers. The calculation is

performed by a three stage process. The first two stages take

500ns each and the third stage takes 250ns. When the write to

one of the X1, C or M registers is complete the calculation

process begins. If the write operation involves the update of a

single DAC channel the user is free to write to another register

provided that the write operation doesn’t finish until the first

stage calculation is complete, i.e. 500ns after the completion of

the first write operation. If a group of channels is being updated

by a single write operation the first stage calculation will be

repeated for each channel, taking 500ns per channel. In this

case the user should not complete the next write operation until

this time has elapsed.

CHANNEL ADDRESSING AND SPECIAL MODES

If the mode bits are not 00, then the data word D13 to D0 is

written to the device. Address bits A5 to A0 determine which

channel or channels is/are written to, while the mode bits

determine to which register (X1A, X1B, C or M) the data is

written, as shown in Table 8. If data is to be written to the X1A

or X1B register, the setting of the A/B bit in the Control

Register determines which (0

X1A, 1

X1B).

Table 9. Mode Bits

M1

M0

Action

1

1

Write DAC input data (X1A or X1B) register,

depending on Control Register A/B bit.

1

0

Write DAC offset (C) register

0

1

Write DAC gain (M) register

0

0

Special function, used in combination with other

bits of word

The AD5370 has very flexible addressing that allows writing of

data to a single channel, all channels in a group, the same

channel in groups 0 to 4 or groups 1 to 4, or all channels in the

device. Table 10 shows all these address modes.

Table 10. Group and Channel Addressing

This table shows which group(s) and which channel(s) is/are addressed for every combination of address bits A5 to A0.

ADDRESS BITS A5 TO A3

000

001

010

011

100

101

110

111

000

All groups,

all channels

Group 0,

channel 0

Group 1,

channel 0

Group 2,

channel 0

Group 3,

channel 0

Group 4,

channel 0

Groups 0,1,2,3,4

channel 0

Groups 1,2,3,4

channel 0

001

Group 0, all

channels

Group 0,

channel 1

Group 1,

channel 1

Group 2,

channel 1

Group 3,

channel 1

Group 4,

channel 1

Groups 0,1,2,3,4

channel 1

Groups 1,2,3,4

channel 1

010

Group 1, all

channels

Group 0,

channel 2

Group 1,

channel 2

Group 2,

channel 2

Group 3,

channel 2

Group 4,

channel 2

Groups 0,1,2,3,4

channel 2

Groups 1,2,3,4

channel 2

011

Group 2, all

channels

Group 0,

channel 3

Group 1,

channel 3

Group 2,

channel 3

Group 3,

channel 3

Group 4,

channel 3

Groups 0,1,2,3,4

channel 3

Groups 1,2,3,4

channel 3

100

Group 3, all

channels

Group 0,

channel 4

Group 1,

channel 4

Group 2,

channel 4

Group 3,

channel 4

Group 4,

channel 4

Groups 0,1,2,3,4

channel 4

Groups 1,2,3,4

channel 4

101

Group 4, all

channels

Group 0,

channel 5

Group 1,

channel 5

Group 2,

channel 5

Group 3,

channel 5

Group 4,

channel 5

Groups 0,1,2,3,4

channel 5

Groups 1,2,3,4

channel 5

110

Reserved

Group 0,

channel 6

Group 1,

channel 6

Group 2,

channel 6

Group 3,

channel 6

Group 4,

channel 6

Groups 0,1,2,3,4

channel 6

Groups 1,2,3,4

channel 6

ADDRESS

BITS A2 TO

A0

111

Reserved

Group 0,

channel 7

Group 1,

channel 7

Group 2,

channel 7

Group 3,

channel 7

Group 4,

channel 7

Groups 0,1,2,3,4

channel 7

Groups 1,2,3,4

channel 7