AD1981BL

Rev. A | Page 27 of 32

JACK SENSE/AUDIO INTERRUPT/STATUS REGISTER

Index 0x72

Reg

No.

Name

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Default

0x72

Jack

Sense

X

X

X

JS

MT2

JS

MT1

JS

MT0

JS1

EQB

JS0

EQB

JS1

TMR

JS0

TMR

JS1

MD

JS0

MD

JS1

ST

JS0

ST

JS1

INT

JS0

INT

0x0000

All register bits are read/write except for JS0ST and JS1ST, which are read-only.

All registers are not shown, and bits containing an X are assumed to be reserved.

Table 40.

Bit

Mnemonic

Function

JS0INT

JS0 Interrupt

This bit indicates that Pin JS0 has generated an interrupt. This bit remains set until the software

services the JS0 interrupt, that is, JS0 ISR should clear this bit by writing a 0 to it.

The interrupt to the system is an OR combination of this bit and JS1INT.

The actual interrupt implementation is selected by the INTS bit (Register 0x76). It is also possible to

generate a software system interrupt by writing a 1 to this bit.

JS1INT

JS1 Interrupt

This bit indicates that Pin JS1 has generated an interrupt. This bit remains set until the software

services the JS1 interrupt, that is, JS1 ISR should clear this bit by writing a 0 to it. See the JS0INT

description for details.

JS0ST

JS0 State

This bit always reports the logic state of the JS0 pin.

JS1ST

JS1 State

This bit always reports the logic state of the JS1 pin.

JS0MD

JS0 Mode

This bit selects the operation mode for the JS0 pin.

0 = Jack sense mode (default).

1 = Interrupt mode.

JS1MD

JS1 Mode

This bit selects the operation mode for the JS1 pin.

0 = Jack sense mode (default).

1 = Interrupt mode.

JS0TMR

JS0 Timer Enable

If this bit is set to 1, JS0 must be high for >278 ms to be recognized.

JS1TMR

JS1 Timer Enable

If this bit is set to 1, JS1 must be high for >278 ms to be recognized.

JS0EQB

JS0 EQ Bypass Enable

This bit enables JS0 to control the EQ bypass. When this bit is set to 1, JS0 = 1 causes the EQ to be

bypassed.

JS1EQB

JS1 EQ Bypass Enable

This bit enables JS1 to control the EQ bypass. When this bit is set to 1, JS1 = 1 causes the EQ to be

bypassed.

JSMT [2:0]

JS Mute Enable

Selector

These three bits select and enable the jack sense muting action (see Table 41).